Loh Tien Hock 51f366ac85 plat: intel: Fix faulty DDR calibration value ... A DDR calibration value is missing write mask, causing ECC DDR calibration to fail. This patch addresses the issue. ECC should also be scrubbed before MMU initializes, thus the scrubbing is moved to ddr intialization phase. Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com>		2019-02-13 14:39:31 +08:00
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aarch64	plat: intel: Add BL2 support for Stratix 10 SoC	2019-02-04 16:17:24 +08:00
include	plat: intel: Fix faulty DDR calibration value	2019-02-13 14:39:31 +08:00
soc	plat: intel: Fix faulty DDR calibration value	2019-02-13 14:39:31 +08:00
bl2_plat_mem_params_desc.c	plat: intel: Add BL2 support for Stratix 10 SoC	2019-02-04 16:17:24 +08:00
bl2_plat_setup.c	plat: intel: Fix faulty DDR calibration value	2019-02-13 14:39:31 +08:00
plat_delay_timer.c	plat: intel: Add BL2 support for Stratix 10 SoC	2019-02-04 16:17:24 +08:00
plat_storage.c	plat: intel: Add BL2 support for Stratix 10 SoC	2019-02-04 16:17:24 +08:00
platform.mk	plat: intel: Add BL2 support for Stratix 10 SoC	2019-02-04 16:17:24 +08:00
platform_def.h	plat: intel: Add BL2 support for Stratix 10 SoC	2019-02-04 16:17:24 +08:00
stratix10_image_load.c	plat: intel: Add BL2 support for Stratix 10 SoC	2019-02-04 16:17:24 +08:00