Oliver Swede 2d696d1811 plat/arm/board/arm_fpga: Initialize the System Counter ... This sets the frequency of the system counter so that the Delay Timer driver programs the correct value to CNTCRL. This value depends on the FPGA image being used, and is 10MHz for the initial test image. Once configured, the BL31 platform setup sequence then enables the system counter. Signed-off-by: Oliver Swede <oli.swede@arm.com> Change-Id: Ieb036a36fd990f350b5953357424a255b8ac5d5a		2020-03-26 20:40:50 +00:00
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board	plat/arm/board/arm_fpga: Initialize the System Counter	2020-03-26 20:40:50 +00:00
common	Implement SMCCC_ARCH_SOC_ID SMC call	2020-03-17 10:14:35 +00:00
css	juno/sgm: Maximize space allocated to SCP_BL2	2020-03-12 15:12:23 +00:00
soc/common	plat/arm: Sanitise includes	2019-01-25 16:04:10 +00:00