43 lines
981 B
C
43 lines
981 B
C
/*
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* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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#include <arch.h>
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#include "../fpga_def.h"
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#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
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#define PLATFORM_LINKER_ARCH aarch64
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#define PLATFORM_STACK_SIZE UL(0x800)
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#define CACHE_WRITEBACK_SHIFT U(6)
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#define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT)
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#define PLATFORM_CORE_COUNT \
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(FPGA_MAX_CLUSTER_COUNT * FPGA_MAX_CPUS_PER_CLUSTER * FPGA_MAX_PE_PER_CPU)
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#define PLAT_NUM_PWR_DOMAINS (FPGA_MAX_CLUSTER_COUNT + \
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PLATFORM_CORE_COUNT) + 1
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#define BL31_BASE UL(0x80000000)
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#define BL31_LIMIT UL(0x80100000)
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#define PLAT_MAX_RET_STATE 1
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#define PLAT_MAX_OFF_STATE 2
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#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
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#define PLAT_FPGA_HOLD_ENTRY_SHIFT 3
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#define PLAT_FPGA_HOLD_STATE_WAIT 0
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#define PLAT_FPGA_HOLD_STATE_GO 1
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#define PLAT_FPGA_CONSOLE_BAUDRATE 38400
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#endif
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