Hadi Asyrafi b90f207a1d Invalidate dcache build option for bl2 entry at EL3 ... Some of the platform (ie. Agilex) make use of CCU IPs which will only be initialized during bl2_el3_early_platform_setup. Any operation to the cache beforehand will crash the platform. Hence, this will provide an option to skip the data cache invalidation upon bl2 entry at EL3 Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I2c924ed0589a72d0034714c31be8fe57237d1f06		2019-09-12 12:36:31 +00:00
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include	intel: agilex: Clear PLL lostlock bypass mode	2019-08-19 10:56:31 +08:00
soc	Merge "intel: agilex: Clear PLL lostlock bypass mode" into integration	2019-08-28 13:05:51 +00:00
bl2_plat_setup.c	intel: agilex: Fix reliance on hard coded clock information	2019-08-14 19:06:35 +08:00
bl31_plat_setup.c	intel: agilex: Fix BL31 memory mapping	2019-07-30 10:56:38 +08:00
platform.mk	Invalidate dcache build option for bl2 entry at EL3	2019-09-12 12:36:31 +00:00
socfpga_psci.c	intel: agilex: Fix psci power domain off	2019-09-12 15:20:04 +08:00
socfpga_sip_svc.c	intel: Adds support for Agilex platform	2019-07-17 19:06:49 +08:00
socfpga_storage.c	intel: Adds support for Agilex platform	2019-07-17 19:06:49 +08:00