Alexei Fedorov c3e8b0be9b AArch32: Disable Secure Cycle Counter ... This patch changes implementation for disabling Secure Cycle Counter. For ARMv8.5 the counter gets disabled by setting SDCR.SCCD bit on CPU cold/warm boot. For the earlier architectures PMCR register is saved/restored on secure world entry/exit from/to Non-secure state, and cycle counting gets disabled by setting PMCR.DP bit. In 'include\aarch32\arch.h' header file new ARMv8.5-PMU related definitions were added. Change-Id: Ia8845db2ebe8de940d66dff479225a5b879316f8 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>		2019-09-26 15:36:02 +00:00
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aarch32	AArch32: Disable Secure Cycle Counter	2019-09-26 15:36:02 +00:00
sp_min.ld.S	sp_min: allow inclusion of a platform-specific linker script	2019-04-25 13:37:56 +02:00
sp_min.mk	Rename symbols and files relating to CVE-2017-5715	2018-05-23 12:45:48 +01:00
sp_min_main.c	Correct typographical errors	2019-01-15 15:16:02 +00:00
sp_min_private.h	sp_min: make sp_min_warm_entrypoint public	2019-04-25 13:37:56 +02:00
wa_cve_2017_5715_bpiall.S	Rename symbols and files relating to CVE-2017-5715	2018-05-23 12:45:48 +01:00
wa_cve_2017_5715_icache_inv.S	Rename symbols and files relating to CVE-2017-5715	2018-05-23 12:45:48 +01:00