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Joel Hutton dd4cf2c745 Cortex A9:errata 794073 workaround 
On Cortex A9 an errata can cause the processor to violate the rules for
speculative fetches when the MMU is off but branch prediction has not
been disabled. The workaround for this is to execute an Invalidate
Entire Branch Prediction Array (BPIALL) followed by a DSB.

see:http://arminfo.emea.arm.com/help/topic/com.arm.doc.uan0009d/UAN0009_cortex_a9_errata_r4.pdf
for more details.

Change-Id: I9146c1fa7563a79f4e15b6251617b9620a587c93
Signed-off-by: Joel Hutton <Joel.Hutton@arm.com>
 		2019-04-12 10:10:32 +00:00
..
aem_generic.S Make errata reporting mandatory for CPU files 2018-10-29 09:54:32 +00:00
cortex_a5.S Make errata reporting mandatory for CPU files 2018-10-29 09:54:32 +00:00
cortex_a7.S Make errata reporting mandatory for CPU files 2018-10-29 09:54:32 +00:00
cortex_a9.S Cortex A9:errata 794073 workaround 2019-04-12 10:10:32 +00:00
cortex_a12.S Make errata reporting mandatory for CPU files 2018-10-29 09:54:32 +00:00
cortex_a15.S Cortex-A15: Implement workaround for errata 827671 2019-03-13 14:05:47 +00:00
cortex_a17.S Cortex-A17: Implement workaround for errata 852423 2019-03-13 15:40:45 +00:00
cortex_a32.S Make errata reporting mandatory for CPU files 2018-10-29 09:54:32 +00:00
cortex_a53.S Cortex-A53: Workarounds for 819472, 824069 and 827319 2019-02-28 09:56:58 +00:00
cortex_a57.S Cortex-A57: Implement workaround for erratum 817169 2019-02-28 09:56:58 +00:00
cortex_a72.S Sanitise includes across codebase 2019-01-04 10:43:17 +00:00
cpu_helpers.S Fixup register handling in aarch32 reset_handler 2019-03-08 15:35:30 +00:00