Andre Przywara 5f5d076387 Neoverse N1: Introduce workaround for Neoverse N1 erratum 1315703 ... Neoverse N1 erratum 1315703 is a Cat A (rare) erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR2_EL1 system register, which will disable the load-bypass-store feature. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdocpjdoc-466751330-1032/index.html Change-Id: I5c708dbe0efa4daa0bcb6bd9622c5efe19c03af9 Signed-off-by: Andre Przywara <andre.przywara@arm.com>		2019-06-06 14:27:37 +01:00
..
arch	Add support for Branch Target Identification	2019-05-24 14:44:45 +01:00
bl1	BL1: Enable pointer authentication support	2019-02-27 11:58:09 +00:00
bl2	BL2_AT_EL3: Enable pointer authentication support	2019-02-27 11:58:09 +00:00
bl2u	Standardise header guards across codebase	2018-11-08 10:20:19 +00:00
bl31	BL31: Enable pointer authentication support	2019-02-27 11:58:10 +00:00
bl32	sp_min: make sp_min_warm_entrypoint public	2019-04-25 13:37:56 +02:00
common	Add support for Branch Target Identification	2019-05-24 14:44:45 +01:00
drivers	SMMUv3: Abort DMA transactions	2019-05-10 16:09:19 +01:00
dt-bindings	stm32mp1: update device tree files	2019-01-18 15:45:08 +01:00
lib	Neoverse N1: Introduce workaround for Neoverse N1 erratum 1315703	2019-06-06 14:27:37 +01:00
plat	Add option for defining platform DRAM2 base	2019-05-15 11:42:39 +01:00
services	Remove support for the SMC Calling Convention 2.0	2019-01-30 16:01:49 +00:00
tools_share	Sanitise includes across codebase	2019-01-04 10:43:17 +00:00