Louis Mayencourt f1be00da0b Use correct type when reading SCR register ... The Secure Configuration Register is 64-bits in AArch64 and 32-bits in AArch32. Use u_register_t instead of unsigned int to reflect this. Change-Id: I51b69467baba36bf0cfaec2595dc8837b1566934 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>		2020-01-28 11:10:48 +00:00
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arm_gicv3_common.c	Sanitise includes across codebase	2019-01-04 10:43:17 +00:00
gic500.c	GICv3: add functions for save and restore	2017-10-05 16:47:53 +01:00
gic600.c	GIC-600: Fix power up sequence	2019-11-15 08:22:58 +00:00
gic600_multichip.c	GIC-600: Fix include ordering according to the coding style	2019-11-19 11:38:33 +00:00
gic600_multichip_private.h	gic/gic600: add support for multichip configuration	2019-11-11 23:40:23 +05:30
gicv3_helpers.c	GICv3: Allow probe for fewer GICR interfaces than exposed by the frame	2019-02-04 15:42:36 +00:00
gicv3_main.c	Use correct type when reading SCR register	2020-01-28 11:10:48 +00:00
gicv3_private.h	Switch AARCH32/AARCH64 to __aarch64__	2019-08-01 13:45:03 -07:00