Marcin Wojtas 4acd900df6 gicv2: enable configuring IRQ trigger type ... This patch introduces new helper routines that allow configuring the individual IRQs to be edge/level-triggered via GICD_ICFGR registers. This is helpful to modify the default configuration of the non-secure GIC SPI's, which are all set during initialization to be level-sensitive. Change-Id: I23deb4a0381691a686a3cda52405aa1dfd5e56f2 Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>		2018-09-03 15:46:14 +03:00
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bl1	Fix MISRA rule 8.4 Part 1	2018-02-28 17:19:55 +00:00
bl2	Fix MISRA rule 8.5 in common code	2018-04-13 14:01:56 +01:00
bl2u	Fix MISRA rule 8.4 in common code	2018-02-28 17:18:46 +00:00
bl31	libc: Fix all includes in codebase	2018-08-22 10:26:05 +01:00
bl32	Introduce the new BL handover interface	2018-02-26 16:31:10 +00:00
common	libc: Move tf_printf and tf_snprintf to libc	2018-08-22 10:26:05 +01:00
drivers	gicv2: enable configuring IRQ trigger type	2018-09-03 15:46:14 +03:00
dt-bindings	stm32mp1: Add device tree files	2018-07-24 17:18:35 +02:00
lib	libc: Move tf_printf and tf_snprintf to libc	2018-08-22 10:26:05 +01:00
plat	plat: marvell: rename common include file	2018-09-02 14:10:47 +03:00
services	libc: Fix all includes in codebase	2018-08-22 10:26:05 +01:00
tools_share	Make TF UUID RFC 4122 compliant	2018-06-14 14:41:00 +01:00