Puneet Saxena 34a6610aeb Tegra194: memctrl: set reorder depth limit for PCIE blocks ... HW bug in third party PCIE IP - PCIE datapath hangs when there are more than 28 outstanding requests on data backbone for x1 controller. Suggested SW WAR is to limit reorder_depth_limit to 16 for PCIE 1W/2AW/3W clients. Change-Id: Id5448251c35d2a93f66a8b5835ae4044f5cef067 Signed-off-by: Puneet Saxena <puneets@nvidia.com>		2020-01-23 09:01:25 -08:00
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t132	Tegra: introduce plat_enable_console()	2019-11-28 11:14:21 -08:00
t186	Tegra: introduce plat_enable_console()	2019-11-28 11:14:21 -08:00
t194	Tegra194: memctrl: set reorder depth limit for PCIE blocks	2020-01-23 09:01:25 -08:00
t210	plat: nvidia: remove spurious UTF-8 characters at top of platform files	2020-01-09 10:51:25 +01:00