Pali Rohár 5a60efa12a fix(a3k): fix comment about BootROM address range ... A53 AP BootROM is just 16 kB long and is mapped to address range 0xFFFF0000-0xFFFF4000. RVBAR_EL3 register has value 0xFFFF0000. A53 AP BootROM itself is in the BootROM window which is 1 MB long and mapped to address range 0xFFF00000-0xFFFFFFFF. CM3 BootROM is not accessible from A53 core. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I5d4a4c7b1e7550c4738c67a872d341f945d48bbc		2022-02-15 13:21:42 +01:00
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aarch64	fix(plat/marvell/a3720/uart): fix UART parent clock rate determination	2021-06-02 14:19:52 +01:00
include	feat(plat/marvell/a3k): add north and south bridge reset registers	2021-12-02 17:37:58 +01:00
a3700_common.mk	build(plat/marvell): do not print comments on stdout	2021-10-19 16:10:29 +02:00
a3700_ea.c	fix: libc: use long for 64-bit types on aarch64	2021-11-08 14:41:17 +00:00
a3700_sip_svc.c	plat: marvell: armada: modify PLAT_FAMILY name for 37xx SoCs	2020-06-18 20:57:45 +02:00
cm3_system_reset.c	plat: marvell: armada: a3k: support doing system reset via CM3 secure coprocessor	2021-01-05 14:01:51 +01:00
dram_win.c	fix(a3k): fix comment about BootROM address range	2022-02-15 13:21:42 +01:00
io_addr_dec.c	fix(plat/marvell/a3k): fix printing info messages on output	2021-07-16 19:07:44 +01:00
marvell_plat_config.c	plat: marvell: armada: modify PLAT_FAMILY name for 37xx SoCs	2020-06-18 20:57:45 +02:00
plat_cci.c	plat: marvell: armada: a3k: improve 4GB DRAM usage from 3.375 GB to 3.75 GB	2021-01-11 18:59:11 +00:00
plat_pm.c	plat: marvell: armada: a3k: Add new compile option A3720_DB_PM_WAKEUP_SRC	2021-04-27 18:00:03 +02:00