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fix: libc: use long for 64-bit types on aarch64 

Use long instead of long long on aarch64 for 64_t stdint types.
Introduce inttypes.h to properly support printf format specifiers for
fixed width types for such change.

Change-Id: I0bca594687a996fde0a9702d7a383055b99f10a1
Signed-off-by: Scott Branden <scott.branden@broadcom.com>
This commit is contained in:
Scott Branden 2020-08-25 13:49:32 -07:00 committed by Manish Pandey
parent 663461b914
commit 4ce3e99a33
43 changed files with 359 additions and 145 deletions
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6
bl32/tsp/tsp_main.c
View File

@ -5,6 +5,8 @@
*/
#include <assert.h>
#include <inttypes.h>
#include <stdint.h>
#include <arch_features.h>
#include <arch_helpers.h>
@ -271,7 +273,7 @@ tsp_args_t *tsp_cpu_resume_main(uint64_t max_off_pwrlvl,
#if LOG_LEVEL >= LOG_LEVEL_INFO
spin_lock(&console_lock);
INFO("TSP: cpu 0x%lx resumed. maximum off power level %lld\n",
INFO("TSP: cpu 0x%lx resumed. maximum off power level %" PRId64 "\n",
read_mpidr(), max_off_pwrlvl);
INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu resume requests\n",
read_mpidr(),
@ -375,7 +377,7 @@ tsp_args_t *tsp_smc_handler(uint64_t func,
#if LOG_LEVEL >= LOG_LEVEL_INFO
spin_lock(&console_lock);
INFO("TSP: cpu 0x%lx received %s smc 0x%llx\n", read_mpidr(),
INFO("TSP: cpu 0x%lx received %s smc 0x%" PRIx64 "\n", read_mpidr(),
((func >> 31) & 1) == 1 ? "fast" : "yielding",
func);
INFO("TSP: cpu 0x%lx: %d smcs, %d erets\n", read_mpidr(),

12
common/fdt_wrappers.c
View File

@ -8,6 +8,8 @@
#include <assert.h>
#include <errno.h>
#include <inttypes.h>
#include <stdint.h>
#include <string.h>
#include <libfdt.h>
@ -402,7 +404,7 @@ static bool fdtw_xlat_hit(const uint32_t *value, int child_addr_size,
addr_range = fdt_read_prop_cells(value + child_addr_size +
parent_addr_size,
range_size);
VERBOSE("DT: Address %llx mapped to %llx with range %llx\n",
VERBOSE("DT: Address %" PRIx64 " mapped to %" PRIx64 " with range %" PRIx64 "\n",
local_address, parent_address, addr_range);
/* Perform range check */
@ -413,8 +415,8 @@ static bool fdtw_xlat_hit(const uint32_t *value, int child_addr_size,
/* Found hit for the addr range that needs to be translated */
*translated_addr = parent_address + (base_address - local_address);
VERBOSE("DT: child address %llx mapped to %llx in parent bus\n",
local_address, parent_address);
VERBOSE("DT: child address %" PRIx64 "mapped to %" PRIx64 " in parent bus\n",
local_address, parent_address);
return true;
}
@ -470,8 +472,8 @@ static uint64_t fdtw_search_all_xlat_entries(const void *dtb,
next_entry = next_entry + ncells_xlat;
}
INFO("DT: No translation found for address %llx in node %s\n",
base_address, fdt_get_name(dtb, local_bus, NULL));
INFO("DT: No translation found for address %" PRIx64 " in node %s\n",
base_address, fdt_get_name(dtb, local_bus, NULL));
return ILLEGAL_ADDR;
}

6
drivers/brcm/emmc/emmc_csl_sdcard.c
View File

@ -4,9 +4,11 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <inttypes.h>
#include <stddef.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <stddef.h>
#include <arch_helpers.h>
#include <lib/mmio.h>
@ -521,7 +523,7 @@ static int xfer_data(struct sd_handle *handle,
{
int rc = SD_OK;
VERBOSE("XFER: dest: 0x%llx, addr: 0x%x, size: 0x%x bytes\n",
VERBOSE("XFER: dest: 0x%" PRIx64 ", addr: 0x%x, size: 0x%x bytes\n",
(uint64_t)base, addr, length);
if ((length / handle->device->cfg.blockSize) > 1) {

13
drivers/marvell/amb_adec.c
View File

@ -7,6 +7,9 @@
/* AXI to M-Bridge decoding unit driver for Marvell Armada 8K and 8K+ SoCs */
#include <inttypes.h>
#include <stdint.h>
#include <common/debug.h>
#include <lib/mmio.h>
@ -44,10 +47,10 @@ static void amb_check_win(struct addr_map_win *win, uint32_t win_num)
/* make sure the base address is in 16-bit range */
if (win->base_addr > AMB_BASE_ADDR_MASK) {
WARN("Window %d: base address is too big 0x%llx\n",
WARN("Window %d: base address is too big 0x%" PRIx64 "\n",
win_num, win->base_addr);
win->base_addr = AMB_BASE_ADDR_MASK;
WARN("Set the base address to 0x%llx\n", win->base_addr);
WARN("Set the base address to 0x%" PRIx64 "\n", win->base_addr);
}
base_addr = win->base_addr << AMB_BASE_OFFSET;
@ -57,15 +60,15 @@ static void amb_check_win(struct addr_map_win *win, uint32_t win_num)
win->base_addr = ALIGN_UP(base_addr, AMB_WIN_ALIGNMENT_1M);
WARN("Window %d: base address unaligned to 0x%x\n",
win_num, AMB_WIN_ALIGNMENT_1M);
WARN("Align up the base address to 0x%llx\n", win->base_addr);
WARN("Align up the base address to 0x%" PRIx64 "\n", win->base_addr);
}
/* size parameter validity check */
if (!IS_POWER_OF_2(win->win_size)) {
WARN("Window %d: window size is not power of 2 (0x%llx)\n",
WARN("Window %d: window size is not power of 2 (0x%" PRIx64 ")\n",
win_num, win->win_size);
win->win_size = ROUND_UP_TO_POW_OF_2(win->win_size);
WARN("Rounding size to 0x%llx\n", win->win_size);
WARN("Rounding size to 0x%" PRIx64 "\n", win->win_size);
}
}

9
drivers/marvell/ccu.c
View File

@ -7,6 +7,9 @@
/* CCU unit device driver for Marvell AP807, AP807 and AP810 SoCs */
#include <inttypes.h>
#include <stdint.h>
#include <common/debug.h>
#include <drivers/marvell/ccu.h>
#include <lib/mmio.h>
@ -84,7 +87,7 @@ static void dump_ccu(int ap_index)
win_id));
start = ((uint64_t)alr << ADDRESS_SHIFT);
end = (((uint64_t)ahr + 0x10) << ADDRESS_SHIFT);
printf("\tccu%d %02x 0x%016llx 0x%016llx\n",
printf("\tccu%d %02x 0x%016" PRIx64 " 0x%016" PRIx64 "\n",
win_id, target_id, start, end);
}
}
@ -99,14 +102,14 @@ void ccu_win_check(struct addr_map_win *win)
/* check if address is aligned to 1M */
if (IS_NOT_ALIGN(win->base_addr, CCU_WIN_ALIGNMENT)) {
win->base_addr = ALIGN_UP(win->base_addr, CCU_WIN_ALIGNMENT);
NOTICE("%s: Align up the base address to 0x%llx\n",
NOTICE("%s: Align up the base address to 0x%" PRIx64 "\n",
__func__, win->base_addr);
}
/* size parameter validity check */
if (IS_NOT_ALIGN(win->win_size, CCU_WIN_ALIGNMENT)) {
win->win_size = ALIGN_UP(win->win_size, CCU_WIN_ALIGNMENT);
NOTICE("%s: Aligning size to 0x%llx\n",
NOTICE("%s: Aligning size to 0x%" PRIx64 "\n",
__func__, win->win_size);
}
}

4
drivers/marvell/comphy/phy-comphy-cp110.c
View File

@ -8,6 +8,8 @@
/* Marvell CP110 SoC COMPHY unit driver */
#include <errno.h>
#include <inttypes.h>
#include <stdint.h>
#include <common/debug.h>
#include <drivers/delay_timer.h>
@ -102,7 +104,7 @@ static void mvebu_cp110_get_ap_and_cp_nr(uint8_t *ap_nr, uint8_t *cp_nr,
*cp_nr = (((comphy_base & ~0xffffff) - MVEBU_AP_IO_BASE(*ap_nr)) /
MVEBU_CP_OFFSET);
debug("cp_base 0x%llx, ap_io_base 0x%lx, cp_offset 0x%lx\n",
debug("cp_base 0x%" PRIx64 ", ap_io_base 0x%lx, cp_offset 0x%lx\n",
comphy_base, (unsigned long)MVEBU_AP_IO_BASE(*ap_nr),
(unsigned long)MVEBU_CP_OFFSET);
}

9
drivers/marvell/gwin.c
View File

@ -7,6 +7,9 @@
/* GWIN unit device driver for Marvell AP810 SoC */
#include <inttypes.h>
#include <stdint.h>
#include <common/debug.h>
#include <drivers/marvell/gwin.h>
#include <lib/mmio.h>
@ -49,14 +52,14 @@ static void gwin_check(struct addr_map_win *win)
/* The base is always 64M aligned */
if (IS_NOT_ALIGN(win->base_addr, GWIN_ALIGNMENT_64M)) {
win->base_addr &= ~(GWIN_ALIGNMENT_64M - 1);
NOTICE("%s: Align the base address to 0x%llx\n",
NOTICE("%s: Align the base address to 0x%" PRIx64 "\n",
__func__, win->base_addr);
}
/* size parameter validity check */
if (IS_NOT_ALIGN(win->win_size, GWIN_ALIGNMENT_64M)) {
win->win_size = ALIGN_UP(win->win_size, GWIN_ALIGNMENT_64M);
NOTICE("%s: Aligning window size to 0x%llx\n",
NOTICE("%s: Aligning window size to 0x%" PRIx64 "\n",
__func__, win->win_size);
}
}
@ -167,7 +170,7 @@ static void dump_gwin(int ap_index)
alr = (alr >> ADDRESS_LSHIFT) << ADDRESS_RSHIFT;
ahr = mmio_read_32(GWIN_AHR_OFFSET(ap_index, win_num));
ahr = (ahr >> ADDRESS_LSHIFT) << ADDRESS_RSHIFT;
printf("\tgwin %d 0x%016llx 0x%016llx\n",
printf("\tgwin %d 0x%016" PRIx64 " 0x%016" PRIx64 "\n",
(cr >> 8) & 0xF, alr, ahr);
}
}

9
drivers/marvell/io_win.c
View File

@ -7,6 +7,9 @@
/* IO Window unit device driver for Marvell AP807, AP807 and AP810 SoCs */
#include <inttypes.h>
#include <stdint.h>
#include <common/debug.h>
#include <drivers/marvell/io_win.h>
#include <lib/mmio.h>
@ -44,14 +47,14 @@ static void io_win_check(struct addr_map_win *win)
/* check if address is aligned to 1M */
if (IS_NOT_ALIGN(win->base_addr, IO_WIN_ALIGNMENT_1M)) {
win->base_addr = ALIGN_UP(win->base_addr, IO_WIN_ALIGNMENT_1M);
NOTICE("%s: Align up the base address to 0x%llx\n",
NOTICE("%s: Align up the base address to 0x%" PRIx64 "\n",
__func__, win->base_addr);
}
/* size parameter validity check */
if (IS_NOT_ALIGN(win->win_size, IO_WIN_ALIGNMENT_1M)) {
win->win_size = ALIGN_UP(win->win_size, IO_WIN_ALIGNMENT_1M);
NOTICE("%s: Aligning size to 0x%llx\n",
NOTICE("%s: Aligning size to 0x%" PRIx64 "\n",
__func__, win->win_size);
}
}
@ -170,7 +173,7 @@ static void dump_io_win(int ap_index)
win_id));
start = ((uint64_t)alr << ADDRESS_SHIFT);
end = (((uint64_t)ahr + 0x10) << ADDRESS_SHIFT);
printf("\tio-win %d 0x%016llx 0x%016llx\n",
printf("\tio-win %d 0x%016" PRIx64 " 0x%016" PRIx64 "\n",
trgt_id, start, end);
}
}

9
drivers/marvell/iob.c
View File

@ -7,6 +7,9 @@
/* IOW unit device driver for Marvell CP110 and CP115 SoCs */
#include <inttypes.h>
#include <stdint.h>
#include <arch_helpers.h>
#include <common/debug.h>
#include <drivers/marvell/iob.h>
@ -57,7 +60,7 @@ static void iob_win_check(struct addr_map_win *win, uint32_t win_num)
win->base_addr = ALIGN_UP(win->base_addr, IOB_WIN_ALIGNMENT);
ERROR("Window %d: base address unaligned to 0x%x\n",
win_num, IOB_WIN_ALIGNMENT);
printf("Align up the base address to 0x%llx\n",
printf("Align up the base address to 0x%" PRIx64 "\n",
win->base_addr);
}
@ -66,7 +69,7 @@ static void iob_win_check(struct addr_map_win *win, uint32_t win_num)
win->win_size = ALIGN_UP(win->win_size, IOB_WIN_ALIGNMENT);
ERROR("Window %d: window size unaligned to 0x%x\n", win_num,
IOB_WIN_ALIGNMENT);
printf("Aligning size to 0x%llx\n", win->win_size);
printf("Aligning size to 0x%" PRIx64 "\n", win->win_size);
}
}
@ -130,7 +133,7 @@ static void dump_iob(void)
*/
end = start + (16 << 20);
}
printf("iob %02d %s 0x%016llx 0x%016llx\n",
printf("iob %02d %s 0x%016" PRIx64 " 0x%016" PRIx64 "\n",
win_id, iob_target_name[target_id],
start, end);
}

7
drivers/marvell/mc_trustzone/mc_trustzone.c
View File

@ -5,6 +5,9 @@
* https://spdx.org/licenses
*/
#include <inttypes.h>
#include <stdint.h>
#include <common/debug.h>
#include <drivers/marvell/addr_map.h>
#include <lib/mmio.h>
@ -39,7 +42,7 @@ void tz_enable_win(int ap_index, const struct addr_map_win *win, int win_id)
/* map the window size to trustzone register convention */
tz_size = fls(TZ_SIZE(win->win_size));
VERBOSE("%s: window size = 0x%llx maps to tz_size %d\n",
VERBOSE("%s: window size = 0x%" PRIx64 " maps to tz_size %d\n",
__func__, win->win_size, tz_size);
if (tz_size < 0 || tz_size > 31) {
ERROR("Using not allowed size for MC TrustZone window %d!\n",
@ -49,7 +52,7 @@ void tz_enable_win(int ap_index, const struct addr_map_win *win, int win_id)
if (base & 0xfff) {
base = base & ~0xfff;
WARN("Attempt to open MC TZ win. at 0x%llx, truncate to 0x%x\n",
WARN("Attempt to open MC TZ win. at 0x%" PRIx64 ", truncate to 0x%x\n",
win->base_addr, base);
}

4
drivers/mtd/spi-mem/spi_mem.c
View File

@ -5,6 +5,8 @@
*/
#include <assert.h>
#include <inttypes.h>
#include <stdint.h>
#include <libfdt.h>
@ -150,7 +152,7 @@ int spi_mem_exec_op(const struct spi_mem_op *op)
const struct spi_bus_ops *ops = spi_slave.ops;
int ret;
VERBOSE("%s: cmd:%x mode:%d.%d.%d.%d addqr:%llx len:%x\n",
VERBOSE("%s: cmd:%x mode:%d.%d.%d.%d addqr:%" PRIx64 " len:%x\n",
__func__, op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
op->dummy.buswidth, op->data.buswidth,
op->addr.val, op->data.nbytes);

9
drivers/nxp/ddr/nxp-ddr/ddr.c
View File

@ -5,6 +5,7 @@
*/
#include <errno.h>
#include <inttypes.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
@ -850,7 +851,7 @@ long long dram_init(struct ddr_info *priv
priv->ip_rev = ip_rev;
#ifndef CONFIG_STATIC_DDR
INFO("time base %llu ms\n", time_base);
INFO("time base %" PRIu64 " ms\n", time_base);
debug("Parse DIMM SPD(s)\n");
valid_spd_mask = parse_spd(priv);
@ -870,7 +871,7 @@ long long dram_init(struct ddr_info *priv
#endif
time = get_timer_val(time_base);
INFO("Time after parsing SPD %llu ms\n", time);
INFO("Time after parsing SPD %" PRIu64 " ms\n", time);
debug("Synthesize configurations\n");
ret = synthesize_ctlr(priv);
if (ret != 0) {
@ -911,7 +912,7 @@ long long dram_init(struct ddr_info *priv
}
time = get_timer_val(time_base);
INFO("Time before programming controller %llu ms\n", time);
INFO("Time before programming controller %" PRIu64 " ms\n", time);
debug("Program controller registers\n");
ret = write_ddrc_regs(priv);
if (ret != 0) {
@ -924,7 +925,7 @@ long long dram_init(struct ddr_info *priv
print_ddr_info(priv->ddr[0]);
time = get_timer_val(time_base);
INFO("Time used by DDR driver %llu ms\n", time);
INFO("Time used by DDR driver %" PRIu64 " ms\n", time);
return dram_size;
}

21
include/lib/libc/aarch32/inttypes_.h Normal file
View File

@ -0,0 +1,21 @@
/*
* Copyright 2020 Broadcom
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* Portions copyright (c) 2020, ARM Limited and Contributors.
* All rights reserved.
*/
#ifndef INTTYPES__H
#define INTTYPES__H
#define PRId64 "lld" /* int64_t */
#define PRIi64 "lli" /* int64_t */
#define PRIo64 "llo" /* int64_t */
#define PRIu64 "llu" /* uint64_t */
#define PRIx64 "llx" /* uint64_t */
#define PRIX64 "llX" /* uint64_t */
#endif /* INTTYPES__H */

28
include/lib/libc/aarch32/stdint_.h Normal file
View File

@ -0,0 +1,28 @@
/*
* Copyright 2020 Broadcom
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* Portions copyright (c) 2020, ARM Limited and Contributors.
* All rights reserved.
*/
#ifndef STDINT__H
#define STDINT__H
#define INT64_MAX LLONG_MAX
#define INT64_MIN LLONG_MIN
#define UINT64_MAX ULLONG_MAX
#define INT64_C(x) x ## LL
#define UINT64_C(x) x ## ULL
typedef long long int64_t;
typedef unsigned long long uint64_t;
typedef long long int64_least_t;
typedef unsigned long long uint64_least_t;
typedef long long int64_fast_t;
typedef unsigned long long uint64_fast_t;
#endif

21
include/lib/libc/aarch64/inttypes_.h Normal file
View File

@ -0,0 +1,21 @@
/*
* Copyright 2020 Broadcom
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* Portions copyright (c) 2020, ARM Limited and Contributors.
* All rights reserved.
*/
#ifndef INTTYPES__H
#define INTTYPES__H
#define PRId64 "ld" /* int64_t */
#define PRIi64 "li" /* int64_t */
#define PRIo64 "lo" /* int64_t */
#define PRIu64 "lu" /* uint64_t */
#define PRIx64 "lx" /* uint64_t */
#define PRIX64 "lX" /* uint64_t */
#endif /* INTTYPES__H */

31
include/lib/libc/aarch64/stdint_.h Normal file
View File

@ -0,0 +1,31 @@
/*
* Copyright 2020 Broadcom
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* Portions copyright (c) 2020, ARM Limited and Contributors.
* All rights reserved.
*/
#ifndef STDINT__H
#define STDINT__H
#define INT64_MAX LONG_MAX
#define INT64_MIN LONG_MIN
#define UINT64_MAX ULONG_MAX
#define INT64_C(x) x ## L
#define UINT64_C(x) x ## UL
typedef long int64_t;
typedef unsigned long uint64_t;
typedef long int64_least_t;
typedef unsigned long uint64_least_t;
typedef long int64_fast_t;
typedef unsigned long uint64_fast_t;
typedef __int128 int128_t;
typedef unsigned __int128 uint128_t;
#endif

47
include/lib/libc/inttypes.h Normal file
View File

@ -0,0 +1,47 @@
/*
* Copyright 2020 Broadcom
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* Portions copyright (c) 2020, ARM Limited and Contributors.
* All rights reserved.
*/
#ifndef INTTYPES_H
#define INTTYPES_H
#include <inttypes_.h>
#include <stdint.h>
#define PRId8 "d" /* int8_t */
#define PRId16 "d" /* int16_t */
#define PRId32 "d" /* int32_t */
#define PRIdPTR "d" /* intptr_t */
#define PRIi8 "i" /* int8_t */
#define PRIi16 "i" /* int16_t */
#define PRIi32 "i" /* int32_t */
#define PRIiPTR "i" /* intptr_t */
#define PRIo8 "o" /* int8_t */
#define PRIo16 "o" /* int16_t */
#define PRIo32 "o" /* int32_t */
#define PRIoPTR "o" /* intptr_t */
#define PRIu8 "u" /* uint8_t */
#define PRIu16 "u" /* uint16_t */
#define PRIu32 "u" /* uint32_t */
#define PRIuPTR "u" /* uintptr_t */
#define PRIx8 "x" /* uint8_t */
#define PRIx16 "x" /* uint16_t */
#define PRIx32 "x" /* uint32_t */
#define PRIxPTR "x" /* uintptr_t */
#define PRIX8 "X" /* uint8_t */
#define PRIX16 "X" /* uint16_t */
#define PRIX32 "X" /* uint32_t */
#define PRIXPTR "X" /* uintptr_t */
#endif

18
include/lib/libc/stdint.h
View File

@ -12,6 +12,7 @@
#define STDINT_H
#include <limits.h>
#include <stdint_.h>
#define INT8_MAX CHAR_MAX
#define INT8_MIN CHAR_MIN
@ -25,10 +26,6 @@
#define INT32_MIN INT_MIN
#define UINT32_MAX UINT_MAX
#define INT64_MAX LLONG_MAX
#define INT64_MIN LLONG_MIN
#define UINT64_MAX ULLONG_MAX
#define INT_LEAST8_MIN INT8_MIN
#define INT_LEAST8_MAX INT8_MAX
#define UINT_LEAST8_MAX UINT8_MAX
@ -77,12 +74,10 @@
#define INT8_C(x) x
#define INT16_C(x) x
#define INT32_C(x) x
#define INT64_C(x) x ## LL
#define UINT8_C(x) x
#define UINT16_C(x) x
#define UINT32_C(x) x ## U
#define UINT64_C(x) x ## ULL
#define INTMAX_C(x) x ## LL
#define UINTMAX_C(x) x ## ULL
@ -90,32 +85,26 @@
typedef signed char int8_t;
typedef short int16_t;
typedef int int32_t;
typedef long long int64_t;
typedef unsigned char uint8_t;
typedef unsigned short uint16_t;
typedef unsigned int uint32_t;
typedef unsigned long long uint64_t;
typedef signed char int8_least_t;
typedef short int16_least_t;
typedef int int32_least_t;
typedef long long int64_least_t;
typedef unsigned char uint8_least_t;
typedef unsigned short uint16_least_t;
typedef unsigned int uint32_least_t;
typedef unsigned long long uint64_least_t;
typedef int int8_fast_t;
typedef int int16_fast_t;
typedef int int32_fast_t;
typedef long long int64_fast_t;
typedef unsigned int uint8_fast_t;
typedef unsigned int uint16_fast_t;
typedef unsigned int uint32_fast_t;
typedef unsigned long long uint64_fast_t;
typedef long intptr_t;
typedef unsigned long uintptr_t;
@ -130,9 +119,4 @@ typedef unsigned long long uintmax_t;
typedef long register_t;
typedef unsigned long u_register_t;
#ifdef __aarch64__
typedef __int128 int128_t;
typedef unsigned __int128 uint128_t;
#endif /* __aarch64__ */
#endif /* STDINT_H */

4
lib/bl_aux_params/bl_aux_params.c
View File

@ -3,6 +3,8 @@
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <inttypes.h>
#include <stdint.h>
#include <common/debug.h>
#include <lib/coreboot.h>
@ -25,7 +27,7 @@ void bl_aux_params_parse(u_register_t head,
break;
#endif
default:
ERROR("Ignoring unknown BL aux parameter: 0x%llx",
ERROR("Ignoring unknown BL aux parameter: 0x%" PRIx64,
p->type);
break;
}

4
lib/extensions/amu/aarch64/amu.c
View File

@ -6,7 +6,9 @@
#include <assert.h>
#include <cdefs.h>
#include <inttypes.h>
#include <stdbool.h>
#include <stdint.h>
#include "../amu_private.h"
#include <arch.h>
@ -343,7 +345,7 @@ static bool amu_group0_voffset_supported(uint64_t idx)
default:
ERROR("AMU: can't set up virtual offset for unknown "
"architected counter %llu!\n", idx);
"architected counter %" PRIu64 "!\n", idx);
panic();
}

5
plat/arm/board/fvp/fconf/fconf_hw_config_getter.c
View File

@ -5,6 +5,9 @@
*/
#include <assert.h>
#include <inttypes.h>
#include <stdint.h>
#include <common/debug.h>
#include <common/fdt_wrappers.h>
#include <fconf_hw_config_getter.h>
@ -229,7 +232,7 @@ int fconf_populate_uart_config(uintptr_t config)
uart_serial_config.uart_base = translated_addr;
VERBOSE("FCONF: UART serial device base address: %llx\n",
VERBOSE("FCONF: UART serial device base address: %" PRIx64 "\n",
uart_serial_config.uart_base);
/*

6
plat/common/aarch64/plat_common.c
View File

@ -5,6 +5,8 @@
*/
#include <assert.h>
#include <inttypes.h>
#include <stdint.h>
#include <arch_helpers.h>
#include <drivers/console.h>
@ -53,7 +55,7 @@ unsigned int platform_core_pos_helper(unsigned long mpidr)
*/
void plat_sdei_handle_masked_trigger(uint64_t mpidr, unsigned int intr)
{
WARN("Spurious SDEI interrupt %u on masked PE %llx\n", intr, mpidr);
WARN("Spurious SDEI interrupt %u on masked PE %" PRIx64 "\n", intr, mpidr);
}
/*
@ -93,7 +95,7 @@ void plat_default_ea_handler(unsigned int ea_reason, uint64_t syndrome, void *co
ERROR_NL();
ERROR("Unhandled External Abort received on 0x%lx from %s\n",
read_mpidr_el1(), get_el_str(level));
ERROR("exception reason=%u syndrome=0x%llx\n", ea_reason, syndrome);
ERROR("exception reason=%u syndrome=0x%" PRIx64 "\n", ea_reason, syndrome);
#if HANDLE_EA_EL3_FIRST
/* Skip backtrace for lower EL */
if (level != MODE_EL3) {

8
plat/common/plat_spmd_manifest.c
View File

@ -6,8 +6,10 @@
#include <assert.h>
#include <errno.h>
#include <string.h>
#include <inttypes.h>
#include <libfdt.h>
#include <stdint.h>
#include <string.h>
#include <common/bl_common.h>
#include <common/debug.h>
@ -80,8 +82,8 @@ static int manifest_parse_attribute(spmc_manifest_attribute_t *attr,
VERBOSE(" version: %u.%u\n", attr->major_version, attr->minor_version);
VERBOSE(" spmc_id: 0x%x\n", attr->spmc_id);
VERBOSE(" binary_size: 0x%x\n", attr->binary_size);
VERBOSE(" load_address: 0x%llx\n", attr->load_address);
VERBOSE(" entrypoint: 0x%llx\n", attr->entrypoint);
VERBOSE(" load_address: 0x%" PRIx64 "\n", attr->load_address);
VERBOSE(" entrypoint: 0x%" PRIx64 "\n", attr->entrypoint);
return 0;
}

4
plat/hisilicon/hikey/hikey_bl1_setup.c
View File

@ -6,6 +6,8 @@
#include <assert.h>
#include <errno.h>
#include <inttypes.h>
#include <stdint.h>
#include <string.h>
#include <arch_helpers.h>
@ -155,7 +157,7 @@ void bl1_plat_set_ep_info(unsigned int image_id,
__asm__ volatile ("msr cpacr_el1, %0" : : "r"(data));
__asm__ volatile ("mrs %0, cpacr_el1" : "=r"(data));
} while ((data & (3 << 20)) != (3 << 20));
INFO("cpacr_el1:0x%llx\n", data);
INFO("cpacr_el1:0x%" PRIx64 "\n", data);
ep_info->args.arg0 = 0xffff & read_mpidr();
ep_info->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX,

4
plat/hisilicon/poplar/bl31_plat_setup.c
View File

@ -6,7 +6,9 @@
#include <assert.h>
#include <errno.h>
#include <inttypes.h>
#include <stddef.h>
#include <stdint.h>
#include <string.h>
#include <platform_def.h>
@ -130,6 +132,6 @@ void bl31_plat_arch_setup(void)
BL_COHERENT_RAM_BASE,
BL_COHERENT_RAM_END);
INFO("Boot BL33 from 0x%lx for %llu Bytes\n",
INFO("Boot BL33 from 0x%lx for %" PRIu64 " Bytes\n",
bl33_image_ep_info.pc, bl33_image_ep_info.args.arg2);
}

24
plat/imx/imx8qm/imx8qm_bl31_setup.c
View File

@ -5,6 +5,8 @@
*/
#include <assert.h>
#include <inttypes.h>
#include <stdint.h>
#include <stdbool.h>
#include <platform_def.h>
@ -261,14 +263,14 @@ void mx8_partition_resources(void)
err = sc_rm_get_memreg_info(ipc_handle, mr, &start, &end);
if (err)
ERROR("Memreg get info failed, %u\n", mr);
NOTICE("Memreg %u 0x%llx -- 0x%llx\n", mr, start, end);
NOTICE("Memreg %u 0x%" PRIx64 " -- 0x%" PRIx64 "\n", mr, start, end);
if (BL31_BASE >= start && (BL31_LIMIT - 1) <= end) {
mr_record = mr; /* Record the mr for ATF running */
} else {
err = sc_rm_assign_memreg(ipc_handle, os_part, mr);
if (err)
ERROR("Memreg assign failed, 0x%llx -- 0x%llx, \
err %d\n", start, end, err);
ERROR("Memreg assign failed, 0x%" PRIx64 " -- 0x%" PRIx64 ", \
err %d\n", start, end, err);
}
}
}
@ -280,23 +282,23 @@ void mx8_partition_resources(void)
if ((BL31_LIMIT - 1) < end) {
err = sc_rm_memreg_alloc(ipc_handle, &mr, BL31_LIMIT, end);
if (err)
ERROR("sc_rm_memreg_alloc failed, 0x%llx -- 0x%llx\n",
(sc_faddr_t)BL31_LIMIT, end);
ERROR("sc_rm_memreg_alloc failed, 0x%" PRIx64 " -- 0x%" PRIx64 "\n",
(sc_faddr_t)BL31_LIMIT, end);
err = sc_rm_assign_memreg(ipc_handle, os_part, mr);
if (err)
ERROR("Memreg assign failed, 0x%llx -- 0x%llx\n",
(sc_faddr_t)BL31_LIMIT, end);
ERROR("Memreg assign failed, 0x%" PRIx64 " -- 0x%" PRIx64 "\n",
(sc_faddr_t)BL31_LIMIT, end);
}
if (start < (BL31_BASE - 1)) {
err = sc_rm_memreg_alloc(ipc_handle, &mr, start, BL31_BASE - 1);
if (err)
ERROR("sc_rm_memreg_alloc failed, 0x%llx -- 0x%llx\n",
start, (sc_faddr_t)BL31_BASE - 1);
ERROR("sc_rm_memreg_alloc failed, 0x%" PRIx64 " -- 0x%" PRIx64 "\n",
start, (sc_faddr_t)BL31_BASE - 1);
err = sc_rm_assign_memreg(ipc_handle, os_part, mr);
if (err)
ERROR("Memreg assign failed, 0x%llx -- 0x%llx\n",
start, (sc_faddr_t)BL31_BASE - 1);
ERROR("Memreg assign failed, 0x%" PRIx64 " -- 0x%" PRIx64 "\n",
start, (sc_faddr_t)BL31_BASE - 1);
}
}

24
plat/imx/imx8qx/imx8qx_bl31_setup.c
View File

@ -5,7 +5,9 @@
*/
#include <assert.h>
#include <inttypes.h>
#include <stdbool.h>
#include <stdint.h>
#include <platform_def.h>
@ -238,14 +240,14 @@ void imx8_partition_resources(void)
if (err)
ERROR("Memreg get info failed, %u\n", mr);
NOTICE("Memreg %u 0x%llx -- 0x%llx\n", mr, start, end);
NOTICE("Memreg %u 0x%" PRIx64 " -- 0x%" PRIx64 "\n", mr, start, end);
if (BL31_BASE >= start && (BL31_LIMIT - 1) <= end) {
mr_record = mr; /* Record the mr for ATF running */
} else {
err = sc_rm_assign_memreg(ipc_handle, os_part, mr);
if (err)
ERROR("Memreg assign failed, 0x%llx -- 0x%llx, \
err %d\n", start, end, err);
ERROR("Memreg assign failed, 0x%" PRIx64 " -- 0x%" PRIx64 ", \
err %d\n", start, end, err);
}
}
}
@ -257,23 +259,23 @@ void imx8_partition_resources(void)
if ((BL31_LIMIT - 1) < end) {
err = sc_rm_memreg_alloc(ipc_handle, &mr, BL31_LIMIT, end);
if (err)
ERROR("sc_rm_memreg_alloc failed, 0x%llx -- 0x%llx\n",
(sc_faddr_t)BL31_LIMIT, end);
ERROR("sc_rm_memreg_alloc failed, 0x%" PRIx64 " -- 0x%" PRIx64 "\n",
(sc_faddr_t)BL31_LIMIT, end);
err = sc_rm_assign_memreg(ipc_handle, os_part, mr);
if (err)
ERROR("Memreg assign failed, 0x%llx -- 0x%llx\n",
(sc_faddr_t)BL31_LIMIT, end);
ERROR("Memreg assign failed, 0x%" PRIx64 " -- 0x%" PRIx64 "\n",
(sc_faddr_t)BL31_LIMIT, end);
}
if (start < (BL31_BASE - 1)) {
err = sc_rm_memreg_alloc(ipc_handle, &mr, start, BL31_BASE - 1);
if (err)
ERROR("sc_rm_memreg_alloc failed, 0x%llx -- 0x%llx\n",
start, (sc_faddr_t)BL31_BASE - 1);
ERROR("sc_rm_memreg_alloc failed, 0x%" PRIx64 " -- 0x%" PRIx64 "\n",
start, (sc_faddr_t)BL31_BASE - 1);
err = sc_rm_assign_memreg(ipc_handle, os_part, mr);
if (err)
ERROR("Memreg assign failed, 0x%llx -- 0x%llx\n",
start, (sc_faddr_t)BL31_BASE - 1);
ERROR("Memreg assign failed, 0x%" PRIx64 " -- 0x%" PRIx64 "\n",
start, (sc_faddr_t)BL31_BASE - 1);
}
}

6
plat/marvell/armada/a3k/common/a3700_ea.c
View File

@ -4,6 +4,10 @@
* SPDX-License-Identifier: BSD-3-Clause
* https://spdx.org/licenses
*/
#include <inttypes.h>
#include <stdint.h>
#include <common/bl_common.h>
#include <common/debug.h>
#include <arch_helpers.h>
@ -72,7 +76,7 @@ void plat_ea_handler(unsigned int ea_reason, uint64_t syndrome, void *cookie,
syndrome == A53_SERR_INT_AXI_SLVERR_ON_EXTERNAL_ACCESS) {
ERROR_NL();
ERROR("Ignoring Asynchronous External Abort with"
" syndrome 0x%llx received on 0x%lx from %s\n",
" syndrome 0x%" PRIx64 " received on 0x%lx from %s\n",
syndrome, read_mpidr_el1(), get_el_str(level));
ERROR("SError interrupt: AXI SLVERR on external access\n");
ERROR("This indicates a bug in pci-aardvark.c driver\n");

7
plat/nvidia/tegra/common/tegra_bl31_setup.c
View File

@ -7,6 +7,7 @@
#include <assert.h>
#include <errno.h>
#include <inttypes.h>
#include <stddef.h>
#include <string.h>
@ -336,7 +337,7 @@ int32_t bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes)
* Sanity check the input values
*/
if ((base == 0U) || (size_in_bytes == 0U)) {
ERROR("NS address 0x%llx (%lld bytes) is invalid\n",
ERROR("NS address 0x%" PRIx64 " (%" PRId64 " bytes) is invalid\n",
base, size_in_bytes);
return -EINVAL;
}
@ -347,7 +348,7 @@ int32_t bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes)
if ((base < TEGRA_DRAM_BASE) || (base >= TEGRA_DRAM_END) ||
(end > TEGRA_DRAM_END)) {
ERROR("NS address 0x%llx is out-of-bounds!\n", base);
ERROR("NS address 0x%" PRIx64 " is out-of-bounds!\n", base);
return -EFAULT;
}
@ -356,7 +357,7 @@ int32_t bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes)
* to check if the NS DRAM range overlaps the TZDRAM aperture.
*/
if ((base < (uint64_t)TZDRAM_END) && (end > tegra_bl31_phys_base)) {
ERROR("NS address 0x%llx overlaps TZDRAM!\n", base);
ERROR("NS address 0x%" PRIx64 " overlaps TZDRAM!\n", base);
return -ENOTSUP;
}

4
plat/nvidia/tegra/soc/t186/drivers/mce/mce.c
View File

@ -7,6 +7,8 @@
#include <assert.h>
#include <errno.h>
#include <inttypes.h>
#include <stdint.h>
#include <string.h>
#include <arch.h>
@ -341,7 +343,7 @@ int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1,
break;
default:
ERROR("unknown MCE command (%llu)\n", cmd);
ERROR("unknown MCE command (%" PRIu64 ")\n", cmd);
ret = EINVAL;
break;
}

4
plat/nvidia/tegra/soc/t194/drivers/mce/mce.c
View File

@ -16,8 +16,10 @@
#include <mce_private.h>
#include <platform_def.h>
#include <stdbool.h>
#include <stdint.h>
#include <string.h>
#include <errno.h>
#include <inttypes.h>
#include <t194_nvg.h>
#include <tegra_def.h>
#include <tegra_platform.h>
@ -69,7 +71,7 @@ int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1,
break;
default:
ERROR("unknown MCE command (%llu)\n", cmd);
ERROR("unknown MCE command (%" PRIu64 ")\n", cmd);
ret = -EINVAL;
break;
}

7
plat/nvidia/tegra/soc/t194/plat_ras.c
View File

@ -4,6 +4,7 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <inttypes.h>
#include <stdbool.h>
#include <stdint.h>
@ -54,7 +55,7 @@ static void tegra194_ea_handler(unsigned int ea_reason, uint64_t syndrome,
ras_lock();
ERROR("MPIDR 0x%lx: exception reason=%u syndrome=0x%llx\n",
ERROR("MPIDR 0x%lx: exception reason=%u syndrome=0x%" PRIx64 "\n",
read_mpidr(), ea_reason, syndrome);
/* Call RAS EA handler */
@ -146,7 +147,7 @@ void tegra194_ras_enable(void)
/* enable the supported errors */
err_ctrl |= err_fr;
VERBOSE("errselr_el1:0x%x, erxfr:0x%llx, err_ctrl:0x%llx\n",
VERBOSE("errselr_el1:0x%x, erxfr:0x%" PRIx64 ", err_ctrl:0x%" PRIx64 "\n",
idx_start + j, err_fr, err_ctrl);
/* enable specified errors, or set to 0 if no supported error */
@ -288,7 +289,7 @@ static int32_t tegra194_ras_node_handler(uint32_t errselr, const char *name,
/* keep the log print same as linux arm64_ras driver. */
ERROR("**************************************\n");
ERROR("RAS Error in %s, ERRSELR_EL1=0x%x:\n", name, errselr);
ERROR("\tStatus = 0x%llx\n", status);
ERROR("\tStatus = 0x%" PRIx64 "\n", status);
/* Print uncorrectable errror information. */
if (ERR_STATUS_GET_FIELD(status, UE) != 0U) {

5
plat/nvidia/tegra/soc/t210/plat_sip_calls.c
View File

@ -5,6 +5,9 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <inttypes.h>
#include <stdint.h>
#include <arch.h>
#include <arch_helpers.h>
#include <assert.h>
@ -71,7 +74,7 @@ int plat_sip_handler(uint32_t smc_fid,
case PMC_CRYPTO_OP_0:
case PMC_TSC_MULT_0:
case PMC_STICKY_BIT:
ERROR("%s: error offset=0x%llx\n", __func__, x2);
ERROR("%s: error offset=0x%" PRIx64 "\n", __func__, x2);
return -EFAULT;
default:
/* Valid register */

6
plat/nxp/common/setup/ls_bl31_setup.c
View File

@ -6,6 +6,8 @@
*/
#include <assert.h>
#include <inttypes.h>
#include <stdint.h>
#ifdef LS_EL3_INTERRUPT_HANDLER
#include <ls_interrupt_mgmt.h>
@ -126,7 +128,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
loc_dram_regions_info->num_dram_regions;
dram_regions_info.total_dram_size =
loc_dram_regions_info->total_dram_size;
VERBOSE("Number of DRAM Regions = %llx\n",
VERBOSE("Number of DRAM Regions = %" PRIx64 "\n",
dram_regions_info.num_dram_regions);
for (i = 0; i < dram_regions_info.num_dram_regions;
@ -135,7 +137,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
loc_dram_regions_info->region[i].addr;
dram_regions_info.region[i].size =
loc_dram_regions_info->region[i].size;
VERBOSE("DRAM%d Size = %llx\n", i,
VERBOSE("DRAM%d Size = %" PRIx64 "\n", i,
dram_regions_info.region[i].size);
}
rcw_porsr1 = bl31_image_ep_info.args.arg4;

6
plat/renesas/rcar/bl2_plat_setup.c
View File

@ -4,6 +4,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <inttypes.h>
#include <stdint.h>
#include <string.h>
#include <libfdt.h>
@ -622,7 +624,7 @@ static void bl2_add_dram_entry(uint64_t start, uint64_t size)
return;
err:
NOTICE("BL2: Cannot add memory node [%llx - %llx] to FDT (ret=%i)\n",
NOTICE("BL2: Cannot add memory node [%" PRIx64 " - %" PRIx64 "] to FDT (ret=%i)\n",
start, start + size - 1, ret);
panic();
}
@ -638,7 +640,7 @@ static void bl2_advertise_dram_entries(uint64_t dram_config[8])
if (!size)
continue;
NOTICE("BL2: CH%d: %llx - %llx, %lld %siB\n",
NOTICE("BL2: CH%d: %" PRIx64 " - %" PRIx64 ", %" PRId64 " %siB\n",
chan, start, start + size - 1,
(size >> 30) ? : size >> 20,
(size >> 30) ? "G" : "M");

4
plat/renesas/rzg/bl2_plat_setup.c
View File

@ -4,6 +4,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <inttypes.h>
#include <stdint.h>
#include <string.h>
#include <arch_helpers.h>
@ -531,7 +533,7 @@ static void bl2_advertise_dram_entries(uint64_t dram_config[8])
continue;
}
NOTICE("BL2: CH%d: %llx - %llx, %lld %siB\n",
NOTICE("BL2: CH%d: %" PRIx64 " - %" PRIx64 ", %" PRId64 " %siB\n",
chan, start, start + size - 1U,
(size >> 30) ? : size >> 20,
(size >> 30) ? "G" : "M");

4
plat/rpi/rpi4/rpi4_bl31_setup.c
View File

@ -5,6 +5,8 @@
*/
#include <assert.h>
#include <inttypes.h>
#include <stdint.h>
#include <libfdt.h>
@ -234,7 +236,7 @@ static void remove_spintable_memreserve(void *dtb)
fdt_del_mem_rsv(dtb, i);
return;
}
WARN("Keeping unknown /memreserve/ region at 0, size: %lld\n",
WARN("Keeping unknown /memreserve/ region at 0, size: %" PRId64 "\n",
size);
}
}

10
plat/xilinx/common/plat_startup.c
View File

@ -5,6 +5,8 @@
*/
#include <assert.h>
#include <inttypes.h>
#include <stdint.h>
#include <arch_helpers.h>
#include <common/debug.h>
@ -170,12 +172,12 @@ enum fsbl_handoff fsbl_atf_handover(entry_point_info_t *bl32,
(ATFHandoffParams->magic[1] != 'L') ||
(ATFHandoffParams->magic[2] != 'N') ||
(ATFHandoffParams->magic[3] != 'X')) {
ERROR("BL31: invalid ATF handoff structure at %llx\n",
ERROR("BL31: invalid ATF handoff structure at %" PRIx64 "\n",
atf_handoff_addr);
return FSBL_HANDOFF_INVAL_STRUCT;
}
VERBOSE("BL31: ATF handoff params at:0x%llx, entries:%u\n",
VERBOSE("BL31: ATF handoff params at:0x%" PRIx64 ", entries:%u\n",
atf_handoff_addr, ATFHandoffParams->num_entries);
if (ATFHandoffParams->num_entries > FSBL_MAX_PARTITIONS) {
ERROR("BL31: ATF handoff params: too many partitions (%u/%u)\n",
@ -193,7 +195,7 @@ enum fsbl_handoff fsbl_atf_handover(entry_point_info_t *bl32,
int target_estate, target_secure;
int target_cpu, target_endianness, target_el;
VERBOSE("BL31: %zd: entry:0x%llx, flags:0x%llx\n", i,
VERBOSE("BL31: %zd: entry:0x%" PRIx64 ", flags:0x%" PRIx64 "\n", i,
ATFHandoffParams->partition[i].entry_point,
ATFHandoffParams->partition[i].flags);
@ -254,7 +256,7 @@ enum fsbl_handoff fsbl_atf_handover(entry_point_info_t *bl32,
}
}
VERBOSE("Setting up %s entry point to:%llx, el:%x\n",
VERBOSE("Setting up %s entry point to:%" PRIx64 ", el:%x\n",
target_secure == FSBL_FLAGS_SECURE ? "BL32" : "BL33",
ATFHandoffParams->partition[i].entry_point,
target_el);

10
services/spd/trusty/trusty.c
View File

@ -6,8 +6,10 @@
*/
#include <assert.h>
#include <inttypes.h>
#include <lib/xlat_tables/xlat_tables_v2.h>
#include <stdbool.h>
#include <stdint.h>
#include <string.h>
#include <arch_helpers.h>
@ -172,7 +174,7 @@ static uint64_t trusty_set_fiq_handler(void *handle, uint64_t cpu,
struct trusty_cpu_ctx *ctx;
if (cpu >= (uint64_t)PLATFORM_CORE_COUNT) {
ERROR("%s: cpu %lld >= %d\n", __func__, cpu, PLATFORM_CORE_COUNT);
ERROR("%s: cpu %" PRId64 " >= %d\n", __func__, cpu, PLATFORM_CORE_COUNT);
return (uint64_t)SM_ERR_INVALID_PARAMETERS;
}
@ -204,7 +206,7 @@ static uint64_t trusty_fiq_exit(void *handle, uint64_t x1, uint64_t x2, uint64_t
ret = trusty_context_switch(NON_SECURE, SMC_FC_FIQ_EXIT, 0, 0, 0);
if (ret.r0 != 1U) {
INFO("%s(%p) SMC_FC_FIQ_EXIT returned unexpected value, %lld\n",
INFO("%s(%p) SMC_FC_FIQ_EXIT returned unexpected value, %" PRId64 "\n",
__func__, handle, ret.r0);
}
@ -356,7 +358,7 @@ static void trusty_cpu_suspend(uint32_t off)
ret = trusty_context_switch(NON_SECURE, SMC_FC_CPU_SUSPEND, off, 0, 0);
if (ret.r0 != 0U) {
INFO("%s: cpu %d, SMC_FC_CPU_SUSPEND returned unexpected value, %lld\n",
INFO("%s: cpu %d, SMC_FC_CPU_SUSPEND returned unexpected value, %" PRId64 "\n",
__func__, plat_my_core_pos(), ret.r0);
}
}
@ -367,7 +369,7 @@ static void trusty_cpu_resume(uint32_t on)
ret = trusty_context_switch(NON_SECURE, SMC_FC_CPU_RESUME, on, 0, 0);
if (ret.r0 != 0U) {
INFO("%s: cpu %d, SMC_FC_CPU_RESUME returned unexpected value, %lld\n",
INFO("%s: cpu %d, SMC_FC_CPU_RESUME returned unexpected value, %" PRId64 "\n",
__func__, plat_my_core_pos(), ret.r0);
}
}

12
services/std_svc/sdei/sdei_intr_mgmt.c
View File

@ -5,6 +5,8 @@
*/
#include <assert.h>
#include <inttypes.h>
#include <stdint.h>
#include <string.h>
#include <arch_helpers.h>
@ -459,8 +461,8 @@ int sdei_intr_handler(uint32_t intr_raw, uint32_t flags, void *handle,
* Interrupts received while this PE was masked can't be
* dispatched.
*/
SDEI_LOG("interrupt %u on %llx while PE masked\n", map->intr,
mpidr);
SDEI_LOG("interrupt %u on %" PRIx64 " while PE masked\n",
map->intr, mpidr);
if (is_event_shared(map))
sdei_map_lock(map);
@ -531,8 +533,8 @@ int sdei_intr_handler(uint32_t intr_raw, uint32_t flags, void *handle,
if (is_event_shared(map))
sdei_map_unlock(map);
SDEI_LOG("ACK %llx, ev:0x%x ss:%d spsr:%lx ELR:%lx\n", mpidr, map->ev_num,
sec_state, read_spsr_el3(), read_elr_el3());
SDEI_LOG("ACK %" PRIx64 ", ev:0x%x ss:%d spsr:%lx ELR:%lx\n",
mpidr, map->ev_num, sec_state, read_spsr_el3(), read_elr_el3());
ctx = handle;
@ -703,7 +705,7 @@ int sdei_event_complete(bool resume, uint64_t pc)
/* Having done sanity checks, pop dispatch */
(void) pop_dispatch();
SDEI_LOG("EOI:%lx, 0x%x spsr:%lx elr:%lx\n", read_mpidr_el1(),
SDEI_LOG("EOI:%lx, %d spsr:%lx elr:%lx\n", read_mpidr_el1(),
map->ev_num, read_spsr_el3(), read_elr_el3());
/*

48
services/std_svc/sdei/sdei_main.c
View File

@ -6,7 +6,9 @@
#include <arch_helpers.h>
#include <assert.h>
#include <inttypes.h>
#include <stddef.h>
#include <stdint.h>
#include <string.h>
#include <bl31/bl31.h>
@ -961,33 +963,33 @@ uint64_t sdei_smc_handler(uint32_t smc_fid,
case SDEI_VERSION:
SDEI_LOG("> VER\n");
ret = (int64_t) sdei_version();
SDEI_LOG("< VER:%llx\n", ret);
SDEI_LOG("< VER:%" PRIx64 "\n", ret);
SMC_RET1(ctx, ret);
case SDEI_EVENT_REGISTER:
x5 = SMC_GET_GP(ctx, CTX_GPREG_X5);
SDEI_LOG("> REG(n:0x%x e:%llx a:%llx f:%x m:%llx)\n", ev_num,
SDEI_LOG("> REG(n:%d e:%" PRIx64 " a:%" PRIx64 " f:%x m:%" PRIx64 "\n", ev_num,
x2, x3, (int) x4, x5);
ret = sdei_event_register(ev_num, x2, x3, x4, x5);
SDEI_LOG("< REG:%lld\n", ret);
SDEI_LOG("< REG:%" PRId64 "\n", ret);
SMC_RET1(ctx, ret);
case SDEI_EVENT_ENABLE:
SDEI_LOG("> ENABLE(n:%d)\n", (int) x1);
ret = sdei_event_enable(ev_num);
SDEI_LOG("< ENABLE:%lld\n", ret);
SDEI_LOG("< ENABLE:%" PRId64 "\n", ret);
SMC_RET1(ctx, ret);
case SDEI_EVENT_DISABLE:
SDEI_LOG("> DISABLE(n:0x%x)\n", ev_num);
ret = sdei_event_disable(ev_num);
SDEI_LOG("< DISABLE:%lld\n", ret);
SDEI_LOG("< DISABLE:%" PRId64 "\n", ret);
SMC_RET1(ctx, ret);
case SDEI_EVENT_CONTEXT:
SDEI_LOG("> CTX(p:%d):%lx\n", (int) x1, read_mpidr_el1());
ret = sdei_event_context(ctx, (unsigned int) x1);
SDEI_LOG("< CTX:%lld\n", ret);
SDEI_LOG("< CTX:%" PRId64 "\n", ret);
SMC_RET1(ctx, ret);
case SDEI_EVENT_COMPLETE_AND_RESUME:
@ -995,10 +997,10 @@ uint64_t sdei_smc_handler(uint32_t smc_fid,
/* Fallthrough */
case SDEI_EVENT_COMPLETE:
SDEI_LOG("> COMPLETE(r:%u sta/ep:%llx):%lx\n",
(unsigned int) resume, x1, read_mpidr_el1());
SDEI_LOG("> COMPLETE(r:%u sta/ep:%" PRIx64 "):%lx\n",
(unsigned int) resume, x1, read_mpidr_el1());
ret = sdei_event_complete(resume, x1);
SDEI_LOG("< COMPLETE:%llx\n", ret);
SDEI_LOG("< COMPLETE:%" PRIx64 "\n", ret);
/*
* Set error code only if the call failed. If the call
@ -1015,19 +1017,19 @@ uint64_t sdei_smc_handler(uint32_t smc_fid,
case SDEI_EVENT_STATUS:
SDEI_LOG("> STAT(n:0x%x)\n", ev_num);
ret = sdei_event_status(ev_num);
SDEI_LOG("< STAT:%lld\n", ret);
SDEI_LOG("< STAT:%" PRId64 "\n", ret);
SMC_RET1(ctx, ret);
case SDEI_EVENT_GET_INFO:
SDEI_LOG("> INFO(n:0x%x, %d)\n", ev_num, (int) x2);
ret = sdei_event_get_info(ev_num, (int) x2);
SDEI_LOG("< INFO:%lld\n", ret);
SDEI_LOG("< INFO:%" PRId64 "\n", ret);
SMC_RET1(ctx, ret);
case SDEI_EVENT_UNREGISTER:
SDEI_LOG("> UNREG(n:0x%x)\n", ev_num);
ret = sdei_event_unregister(ev_num);
SDEI_LOG("< UNREG:%lld\n", ret);
SDEI_LOG("< UNREG:%" PRId64 "\n", ret);
SMC_RET1(ctx, ret);
case SDEI_PE_UNMASK:
@ -1039,49 +1041,49 @@ uint64_t sdei_smc_handler(uint32_t smc_fid,
case SDEI_PE_MASK:
SDEI_LOG("> MASK:%lx\n", read_mpidr_el1());
ret = sdei_pe_mask();
SDEI_LOG("< MASK:%lld\n", ret);
SDEI_LOG("< MASK:%" PRId64 "\n", ret);
SMC_RET1(ctx, ret);
case SDEI_INTERRUPT_BIND:
SDEI_LOG("> BIND(%d)\n", (int) x1);
ret = sdei_interrupt_bind((unsigned int) x1);
SDEI_LOG("< BIND:%lld\n", ret);
SDEI_LOG("< BIND:%" PRId64 "\n", ret);
SMC_RET1(ctx, ret);
case SDEI_INTERRUPT_RELEASE:
SDEI_LOG("> REL(0x%x)\n", ev_num);
ret = sdei_interrupt_release(ev_num);
SDEI_LOG("< REL:%lld\n", ret);
SDEI_LOG("< REL:%" PRId64 "\n", ret);
SMC_RET1(ctx, ret);
case SDEI_SHARED_RESET:
SDEI_LOG("> S_RESET():%lx\n", read_mpidr_el1());
ret = sdei_shared_reset();
SDEI_LOG("< S_RESET:%lld\n", ret);
SDEI_LOG("< S_RESET:%" PRId64 "\n", ret);
SMC_RET1(ctx, ret);
case SDEI_PRIVATE_RESET:
SDEI_LOG("> P_RESET():%lx\n", read_mpidr_el1());
ret = sdei_private_reset();
SDEI_LOG("< P_RESET:%lld\n", ret);
SDEI_LOG("< P_RESET:%" PRId64 "\n", ret);
SMC_RET1(ctx, ret);
case SDEI_EVENT_ROUTING_SET:
SDEI_LOG("> ROUTE_SET(n:0x%x f:%llx aff:%llx)\n", ev_num, x2, x3);
SDEI_LOG("> ROUTE_SET(n:%d f:%" PRIx64 " aff:%" PRIx64 ")\n", ev_num, x2, x3);
ret = sdei_event_routing_set(ev_num, x2, x3);
SDEI_LOG("< ROUTE_SET:%lld\n", ret);
SDEI_LOG("< ROUTE_SET:%" PRId64 "\n", ret);
SMC_RET1(ctx, ret);
case SDEI_FEATURES:
SDEI_LOG("> FTRS(f:%llx)\n", x1);
SDEI_LOG("> FTRS(f:%" PRIx64 ")\n", x1);
ret = (int64_t) sdei_features((unsigned int) x1);
SDEI_LOG("< FTRS:%llx\n", ret);
SDEI_LOG("< FTRS:%" PRIx64 "\n", ret);
SMC_RET1(ctx, ret);
case SDEI_EVENT_SIGNAL:
SDEI_LOG("> SIGNAL(e:0x%x t:%llx)\n", ev_num, x2);
SDEI_LOG("> SIGNAL(e:%d t:%" PRIx64 ")\n", ev_num, x2);
ret = sdei_signal(ev_num, x2);
SDEI_LOG("< SIGNAL:%lld\n", ret);
SDEI_LOG("< SIGNAL:%" PRId64 "\n", ret);
SMC_RET1(ctx, ret);
default:

18
services/std_svc/spmd/spmd_main.c
View File

@ -6,6 +6,8 @@
#include <assert.h>
#include <errno.h>
#include <inttypes.h>
#include <stdint.h>
#include <string.h>
#include <arch_helpers.h>
@ -49,7 +51,7 @@ spmd_spm_core_context_t *spmd_get_context_by_mpidr(uint64_t mpidr)
int core_idx = plat_core_pos_by_mpidr(mpidr);
if (core_idx < 0) {
ERROR("Invalid mpidr: %llx, returned ID: %d\n", mpidr, core_idx);
ERROR("Invalid mpidr: %" PRIx64 ", returned ID: %d\n", mpidr, core_idx);
panic();
}
@ -156,7 +158,7 @@ static int32_t spmd_init(void)
rc = spmd_spm_core_sync_entry(ctx);
if (rc != 0ULL) {
ERROR("SPMC initialisation failed 0x%llx\n", rc);
ERROR("SPMC initialisation failed 0x%" PRIx64 "\n", rc);
return 0;
}
@ -436,12 +438,12 @@ uint64_t spmd_smc_handler(uint32_t smc_fid,
/* Determine which security state this SMC originated from */
secure_origin = is_caller_secure(flags);
VERBOSE("SPM(%u): 0x%x 0x%llx 0x%llx 0x%llx 0x%llx "
"0x%llx 0x%llx 0x%llx\n",
linear_id, smc_fid, x1, x2, x3, x4,
SMC_GET_GP(handle, CTX_GPREG_X5),
SMC_GET_GP(handle, CTX_GPREG_X6),
SMC_GET_GP(handle, CTX_GPREG_X7));
VERBOSE("SPM(%u): 0x%x 0x%" PRIx64 " 0x%" PRIx64 " 0x%" PRIx64 " 0x%" PRIx64
" 0x%" PRIx64 " 0x%" PRIx64 " 0x%" PRIx64 "\n",
linear_id, smc_fid, x1, x2, x3, x4,
SMC_GET_GP(handle, CTX_GPREG_X5),
SMC_GET_GP(handle, CTX_GPREG_X6),
SMC_GET_GP(handle, CTX_GPREG_X7));
switch (smc_fid) {
case FFA_ERROR:

7
services/std_svc/spmd/spmd_pm.c
View File

@ -6,6 +6,9 @@
#include <assert.h>
#include <errno.h>
#include <inttypes.h>
#include <stdint.h>
#include <lib/el3_runtime/context_mgmt.h>
#include <lib/spinlock.h>
#include "spmd_private.h"
@ -110,7 +113,7 @@ static void spmd_cpu_on_finish_handler(u_register_t unused)
rc = spmd_spm_core_sync_entry(ctx);
if (rc != 0ULL) {
ERROR("%s failed (%llu) on CPU%u\n", __func__, rc,
ERROR("%s failed (%" PRIu64 ") on CPU%u\n", __func__, rc,
linear_id);
ctx->state = SPMC_STATE_OFF;
return;
@ -138,7 +141,7 @@ static int32_t spmd_cpu_off_handler(u_register_t unused)
rc = spmd_spm_core_sync_entry(ctx);
if (rc != 0ULL) {
ERROR("%s failed (%llu) on CPU%u\n", __func__, rc, linear_id);
ERROR("%s failed (%" PRIu64 ") on CPU%u\n", __func__, rc, linear_id);
}
/* Expect a direct message response from the SPMC. */