497 lines
14 KiB
C
497 lines
14 KiB
C
/*
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* Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch.h>
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#include <arch_helpers.h>
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#include <debug.h>
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#include <denver.h>
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#include <mmio.h>
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#include <mce.h>
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#include <sys/errno.h>
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#include <t18x_ari.h>
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/*******************************************************************************
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* Register offsets for ARI request/results
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******************************************************************************/
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#define ARI_REQUEST 0x0
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#define ARI_REQUEST_EVENT_MASK 0x4
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#define ARI_STATUS 0x8
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#define ARI_REQUEST_DATA_LO 0xC
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#define ARI_REQUEST_DATA_HI 0x10
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#define ARI_RESPONSE_DATA_LO 0x14
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#define ARI_RESPONSE_DATA_HI 0x18
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/* Status values for the current request */
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#define ARI_REQ_PENDING 1
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#define ARI_REQ_ONGOING 3
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#define ARI_REQUEST_VALID_BIT (1 << 8)
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#define ARI_EVT_MASK_STANDBYWFI_BIT (1 << 7)
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/*******************************************************************************
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* ARI helper functions
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******************************************************************************/
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static inline uint32_t ari_read_32(uint32_t ari_base, uint32_t reg)
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{
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return mmio_read_32(ari_base + reg);
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}
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static inline void ari_write_32(uint32_t ari_base, uint32_t val, uint32_t reg)
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{
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mmio_write_32(ari_base + reg, val);
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}
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static inline uint32_t ari_get_request_low(uint32_t ari_base)
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{
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return ari_read_32(ari_base, ARI_REQUEST_DATA_LO);
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}
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static inline uint32_t ari_get_request_high(uint32_t ari_base)
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{
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return ari_read_32(ari_base, ARI_REQUEST_DATA_HI);
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}
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static inline uint32_t ari_get_response_low(uint32_t ari_base)
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{
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return ari_read_32(ari_base, ARI_RESPONSE_DATA_LO);
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}
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static inline uint32_t ari_get_response_high(uint32_t ari_base)
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{
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return ari_read_32(ari_base, ARI_RESPONSE_DATA_HI);
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}
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static inline void ari_clobber_response(uint32_t ari_base)
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{
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ari_write_32(ari_base, 0, ARI_RESPONSE_DATA_LO);
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ari_write_32(ari_base, 0, ARI_RESPONSE_DATA_HI);
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}
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static int ari_request_wait(uint32_t ari_base, uint32_t evt_mask, uint32_t req,
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uint32_t lo, uint32_t hi)
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{
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int status;
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/* program the request, event_mask, hi and lo registers */
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ari_write_32(ari_base, lo, ARI_REQUEST_DATA_LO);
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ari_write_32(ari_base, hi, ARI_REQUEST_DATA_HI);
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ari_write_32(ari_base, evt_mask, ARI_REQUEST_EVENT_MASK);
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ari_write_32(ari_base, req | ARI_REQUEST_VALID_BIT, ARI_REQUEST);
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/*
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* For commands that have an event trigger, we should bypass
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* ARI_STATUS polling, since MCE is waiting for SW to trigger
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* the event.
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*/
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if (evt_mask)
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return 0;
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/* NOTE: add timeout check if needed */
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status = ari_read_32(ari_base, ARI_STATUS);
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while (status & (ARI_REQ_ONGOING | ARI_REQ_PENDING))
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status = ari_read_32(ari_base, ARI_STATUS);
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return 0;
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}
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int ari_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time)
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{
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/* check for allowed power state */
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if (state != TEGRA_ARI_CORE_C0 && state != TEGRA_ARI_CORE_C1 &&
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state != TEGRA_ARI_CORE_C6 && state != TEGRA_ARI_CORE_C7) {
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ERROR("%s: unknown cstate (%d)\n", __func__, state);
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return EINVAL;
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}
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/* clean the previous response state */
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ari_clobber_response(ari_base);
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/* Enter the cstate, to be woken up after wake_time (TSC ticks) */
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return ari_request_wait(ari_base, ARI_EVT_MASK_STANDBYWFI_BIT,
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TEGRA_ARI_ENTER_CSTATE, state, wake_time);
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}
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int ari_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccplex,
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uint32_t system, uint8_t sys_state_force, uint32_t wake_mask,
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uint8_t update_wake_mask)
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{
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uint32_t val = 0;
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/* clean the previous response state */
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ari_clobber_response(ari_base);
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/* update CLUSTER_CSTATE? */
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if (cluster)
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val |= (cluster & CLUSTER_CSTATE_MASK) |
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CLUSTER_CSTATE_UPDATE_BIT;
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/* update CCPLEX_CSTATE? */
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if (ccplex)
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val |= (ccplex & CCPLEX_CSTATE_MASK) << CCPLEX_CSTATE_SHIFT |
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CCPLEX_CSTATE_UPDATE_BIT;
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/* update SYSTEM_CSTATE? */
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if (system)
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val |= ((system & SYSTEM_CSTATE_MASK) << SYSTEM_CSTATE_SHIFT) |
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((sys_state_force << SYSTEM_CSTATE_FORCE_UPDATE_SHIFT) |
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SYSTEM_CSTATE_UPDATE_BIT);
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/* update wake mask value? */
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if (update_wake_mask)
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val |= CSTATE_WAKE_MASK_UPDATE_BIT;
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/* set the updated cstate info */
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return ari_request_wait(ari_base, 0, TEGRA_ARI_UPDATE_CSTATE_INFO, val,
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wake_mask);
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}
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int ari_update_crossover_time(uint32_t ari_base, uint32_t type, uint32_t time)
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{
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/* sanity check crossover type */
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if ((type == TEGRA_ARI_CROSSOVER_C1_C6) ||
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(type > TEGRA_ARI_CROSSOVER_CCP3_SC1))
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return EINVAL;
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/* clean the previous response state */
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ari_clobber_response(ari_base);
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/* update crossover threshold time */
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return ari_request_wait(ari_base, 0, TEGRA_ARI_UPDATE_CROSSOVER,
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type, time);
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}
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uint64_t ari_read_cstate_stats(uint32_t ari_base, uint32_t state)
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{
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int ret;
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/* sanity check crossover type */
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if (state == 0)
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return EINVAL;
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/* clean the previous response state */
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ari_clobber_response(ari_base);
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ret = ari_request_wait(ari_base, 0, TEGRA_ARI_CSTATE_STATS, state, 0);
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if (ret != 0)
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return EINVAL;
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return (uint64_t)ari_get_response_low(ari_base);
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}
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int ari_write_cstate_stats(uint32_t ari_base, uint32_t state, uint32_t stats)
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{
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/* clean the previous response state */
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ari_clobber_response(ari_base);
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/* write the cstate stats */
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return ari_request_wait(ari_base, 0, TEGRA_ARI_WRITE_CSTATE_STATS, state,
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stats);
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}
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uint64_t ari_enumeration_misc(uint32_t ari_base, uint32_t cmd, uint32_t data)
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{
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uint64_t resp;
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int ret;
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/* clean the previous response state */
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ari_clobber_response(ari_base);
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/* ARI_REQUEST_DATA_HI is reserved for commands other than 'ECHO' */
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if (cmd != TEGRA_ARI_MISC_ECHO)
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data = 0;
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ret = ari_request_wait(ari_base, 0, TEGRA_ARI_MISC, cmd, data);
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if (ret)
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return (uint64_t)ret;
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/* get the command response */
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resp = ari_get_response_low(ari_base);
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resp |= ((uint64_t)ari_get_response_high(ari_base) << 32);
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return resp;
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}
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int ari_is_ccx_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time)
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{
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int ret;
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/* clean the previous response state */
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ari_clobber_response(ari_base);
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ret = ari_request_wait(ari_base, 0, TEGRA_ARI_IS_CCX_ALLOWED, state & 0x7,
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wake_time);
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if (ret) {
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ERROR("%s: failed (%d)\n", __func__, ret);
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return 0;
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}
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/* 1 = CCx allowed, 0 = CCx not allowed */
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return (ari_get_response_low(ari_base) & 0x1);
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}
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int ari_is_sc7_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time)
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{
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int ret;
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/* check for allowed power state */
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if (state != TEGRA_ARI_CORE_C0 && state != TEGRA_ARI_CORE_C1 &&
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state != TEGRA_ARI_CORE_C6 && state != TEGRA_ARI_CORE_C7) {
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ERROR("%s: unknown cstate (%d)\n", __func__, state);
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return EINVAL;
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}
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/* clean the previous response state */
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ari_clobber_response(ari_base);
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ret = ari_request_wait(ari_base, 0, TEGRA_ARI_IS_SC7_ALLOWED, state,
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wake_time);
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if (ret) {
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ERROR("%s: failed (%d)\n", __func__, ret);
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return 0;
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}
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/* 1 = SC7 allowed, 0 = SC7 not allowed */
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return !!ari_get_response_low(ari_base);
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}
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int ari_online_core(uint32_t ari_base, uint32_t core)
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{
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int cpu = read_mpidr() & MPIDR_CPU_MASK;
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int cluster = (read_mpidr() & MPIDR_CLUSTER_MASK) >>
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MPIDR_AFFINITY_BITS;
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int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK;
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/* construct the current CPU # */
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cpu |= (cluster << 2);
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/* sanity check target core id */
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if ((core >= MCE_CORE_ID_MAX) || (cpu == core)) {
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ERROR("%s: unsupported core id (%d)\n", __func__, core);
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return EINVAL;
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}
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/*
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* The Denver cluster has 2 CPUs only - 0, 1.
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*/
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if (impl == DENVER_IMPL && ((core == 2) || (core == 3))) {
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ERROR("%s: unknown core id (%d)\n", __func__, core);
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return EINVAL;
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}
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/* clean the previous response state */
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ari_clobber_response(ari_base);
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return ari_request_wait(ari_base, 0, TEGRA_ARI_ONLINE_CORE, core, 0);
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}
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int ari_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable)
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{
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int val;
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/* clean the previous response state */
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ari_clobber_response(ari_base);
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/*
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* If the enable bit is cleared, Auto-CC3 will be disabled by setting
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* the SW visible voltage/frequency request registers for all non
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* floorswept cores valid independent of StandbyWFI and disabling
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* the IDLE voltage/frequency request register. If set, Auto-CC3
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* will be enabled by setting the ARM SW visible voltage/frequency
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* request registers for all non floorswept cores to be enabled by
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* StandbyWFI or the equivalent signal, and always keeping the IDLE
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* voltage/frequency request register enabled.
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*/
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val = (((freq & MCE_AUTO_CC3_FREQ_MASK) << MCE_AUTO_CC3_FREQ_SHIFT) |\
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((volt & MCE_AUTO_CC3_VTG_MASK) << MCE_AUTO_CC3_VTG_SHIFT) |\
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(enable ? MCE_AUTO_CC3_ENABLE_BIT : 0));
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return ari_request_wait(ari_base, 0, TEGRA_ARI_CC3_CTRL, val, 0);
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}
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int ari_reset_vector_update(uint32_t ari_base)
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{
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/* clean the previous response state */
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ari_clobber_response(ari_base);
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/*
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* Need to program the CPU reset vector one time during cold boot
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* and SC7 exit
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*/
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ari_request_wait(ari_base, 0, TEGRA_ARI_COPY_MISCREG_AA64_RST, 0, 0);
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return 0;
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}
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int ari_roc_flush_cache_trbits(uint32_t ari_base)
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{
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/* clean the previous response state */
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ari_clobber_response(ari_base);
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return ari_request_wait(ari_base, 0, TEGRA_ARI_ROC_FLUSH_CACHE_TRBITS,
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0, 0);
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}
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int ari_roc_flush_cache(uint32_t ari_base)
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{
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/* clean the previous response state */
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ari_clobber_response(ari_base);
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return ari_request_wait(ari_base, 0, TEGRA_ARI_ROC_FLUSH_CACHE_ONLY,
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0, 0);
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}
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int ari_roc_clean_cache(uint32_t ari_base)
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{
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/* clean the previous response state */
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ari_clobber_response(ari_base);
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return ari_request_wait(ari_base, 0, TEGRA_ARI_ROC_CLEAN_CACHE_ONLY,
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0, 0);
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}
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uint64_t ari_read_write_mca(uint32_t ari_base, mca_cmd_t cmd, uint64_t *data)
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{
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mca_arg_t mca_arg;
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int ret;
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/* Set data (write) */
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mca_arg.data = data ? *data : 0ull;
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/* Set command */
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ari_write_32(ari_base, cmd.input.low, ARI_RESPONSE_DATA_LO);
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ari_write_32(ari_base, cmd.input.high, ARI_RESPONSE_DATA_HI);
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ret = ari_request_wait(ari_base, 0, TEGRA_ARI_MCA, mca_arg.arg.low,
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mca_arg.arg.high);
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if (!ret) {
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mca_arg.arg.low = ari_get_response_low(ari_base);
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mca_arg.arg.high = ari_get_response_high(ari_base);
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if (!mca_arg.err.finish)
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return (uint64_t)mca_arg.err.error;
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if (data) {
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mca_arg.arg.low = ari_get_request_low(ari_base);
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mca_arg.arg.high = ari_get_request_high(ari_base);
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*data = mca_arg.data;
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}
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}
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return 0;
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}
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int ari_update_ccplex_gsc(uint32_t ari_base, uint32_t gsc_idx)
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{
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/* sanity check GSC ID */
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if (gsc_idx > TEGRA_ARI_GSC_VPR_IDX)
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return EINVAL;
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/* clean the previous response state */
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ari_clobber_response(ari_base);
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/*
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* The MCE code will read the GSC carveout value, corrseponding to
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* the ID, from the MC registers and update the internal GSC registers
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* of the CCPLEX.
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*/
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ari_request_wait(ari_base, 0, TEGRA_ARI_UPDATE_CCPLEX_GSC, gsc_idx, 0);
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return 0;
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}
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void ari_enter_ccplex_state(uint32_t ari_base, uint32_t state_idx)
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{
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/* clean the previous response state */
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ari_clobber_response(ari_base);
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/*
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* The MCE will shutdown or restart the entire system
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*/
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(void)ari_request_wait(ari_base, 0, TEGRA_ARI_MISC_CCPLEX, state_idx, 0);
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}
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int ari_read_write_uncore_perfmon(uint32_t ari_base,
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uncore_perfmon_req_t req, uint64_t *data)
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{
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int ret;
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uint32_t val;
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/* clean the previous response state */
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ari_clobber_response(ari_base);
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/* sanity check input parameters */
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if (req.perfmon_command.cmd == UNCORE_PERFMON_CMD_READ && !data) {
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ERROR("invalid parameters\n");
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return EINVAL;
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}
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/*
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* For "write" commands get the value that has to be written
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* to the uncore perfmon registers
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*/
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val = (req.perfmon_command.cmd == UNCORE_PERFMON_CMD_WRITE) ?
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*data : 0;
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ret = ari_request_wait(ari_base, 0, TEGRA_ARI_PERFMON, val, req.data);
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if (ret)
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return ret;
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/* read the command status value */
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req.perfmon_status.val = ari_get_response_high(ari_base) &
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UNCORE_PERFMON_RESP_STATUS_MASK;
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/*
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* For "read" commands get the data from the uncore
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* perfmon registers
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*/
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if ((req.perfmon_status.val == 0) && (req.perfmon_command.cmd ==
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UNCORE_PERFMON_CMD_READ))
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*data = ari_get_response_low(ari_base);
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return (int)req.perfmon_status.val;
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}
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void ari_misc_ccplex(uint32_t ari_base, uint32_t index, uint32_t value)
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{
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/*
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* This invokes the ARI_MISC_CCPLEX commands. This can be
|
|
* used to enable/disable coresight clock gating.
|
|
*/
|
|
|
|
if ((index > TEGRA_ARI_MISC_CCPLEX_CORESIGHT_CG_CTRL) ||
|
|
((index == TEGRA_ARI_MISC_CCPLEX_CORESIGHT_CG_CTRL) &&
|
|
(value > 1))) {
|
|
ERROR("%s: invalid parameters \n", __func__);
|
|
return;
|
|
}
|
|
|
|
/* clean the previous response state */
|
|
ari_clobber_response(ari_base);
|
|
(void)ari_request_wait(ari_base, 0, TEGRA_ARI_MISC_CCPLEX, index, value);
|
|
}
|