Sieu Mun Tang 4837a64093 fix(intel): allow non-secure access to FPGA Crypto Services (FCS) ... Allows non-secure software to access FPGA Crypto Services (FCS) through secure monitor calls (SMC). Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com> Change-Id: I805b3f650abf5e118e2c55e469866d5d0ca68048		2022-05-11 10:02:46 +08:00
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plat_macros.S	intel: Platform common code refactor	2019-08-07 12:19:11 +00:00
platform_def.h	feat(intel): implement timer init divider via cpu frequency. (#1)	2022-05-06 17:37:45 +02:00
socfpga_emac.h	intel: Enable EMAC PHY in Intel FPGA platform	2020-02-25 10:19:51 +08:00
socfpga_f2sdram_manager.h	feat(intel): add support for F2S and S2F bridge SMC with mask to enable, disable and reset bridge	2022-05-05 22:58:03 +08:00
socfpga_fcs.h	feat(intel): single certificate feature enablement	2022-05-11 10:01:54 +08:00
socfpga_handoff.h	intel: Change boot source selection	2020-02-03 14:31:52 +08:00
socfpga_mailbox.h	fix(intel): allow non-secure access to FPGA Crypto Services (FCS)	2022-05-11 10:02:46 +08:00
socfpga_noc.h	feat(intel): enable firewall for OCRAM in BL31	2022-04-28 19:08:35 +08:00
socfpga_private.h	feat(intel): implement timer init divider via cpu frequency. (#1)	2022-05-06 17:37:45 +02:00
socfpga_reset_manager.h	feat(intel): add support for F2S and S2F bridge SMC with mask to enable, disable and reset bridge	2022-05-05 22:58:03 +08:00
socfpga_sip_svc.h	fix(intel): allow non-secure access to FPGA Crypto Services (FCS)	2022-05-11 10:02:46 +08:00
socfpga_system_manager.h	feat(intel): add support for F2S and S2F bridge SMC with mask to enable, disable and reset bridge	2022-05-05 22:58:03 +08:00