Soren Brinkmann 538957d85b zynqmp: Set RESET_TO_BL31 through platform.mk ... ZynqMP only supports builds with RESET_TO_BL31=1. Set this option through the platform makefile on default. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>		2016-09-13 09:19:02 -07:00
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aarch64	zynqmp: Add support for generic_delay_timer	2016-09-13 09:19:02 -07:00
include	zynqmp: Separate code and rodata	2016-07-11 05:25:35 -07:00
pm_service	zynqmp: pm: Added NODE_IPI_RPU_0 node definition in pm_defs	2016-09-13 09:19:02 -07:00
tsp	zynqmp: Separate code and rodata	2016-07-11 05:25:35 -07:00
bl31_zynqmp_setup.c	zynqmp: Separate code and rodata	2016-07-11 05:25:35 -07:00
plat_psci.c	zynqmp: PSCI: Wait for FW completing wake requests	2016-05-25 10:47:03 -07:00
plat_startup.c	zynqmp: Remove double ';'	2016-05-29 09:48:44 -07:00
plat_topology.c	zynqmp: Remove unused/redundant #includes	2016-04-18 07:33:15 -07:00
plat_zynqmp.c	Add support for Xilinx Zynq UltraScale+ MPSOC	2016-04-06 10:44:27 -07:00
platform.mk	zynqmp: Set RESET_TO_BL31 through platform.mk	2016-09-13 09:19:02 -07:00
sip_svc_setup.c	Add support for Xilinx Zynq UltraScale+ MPSOC	2016-04-06 10:44:27 -07:00
zynqmp_def.h	zynqmp: Add option to select between Cadence UARTs	2016-06-15 09:05:11 -07:00
zynqmp_private.h	zynqmp: FSBL->ATF handover	2016-04-25 09:49:59 -07:00