88 lines
3.7 KiB
C
88 lines
3.7 KiB
C
/*
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* Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CORTEX_A57_H__
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#define __CORTEX_A57_H__
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/* Cortex-A57 midr for revision 0 */
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#define CORTEX_A57_MIDR 0x410FD070
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/* Retention timer tick definitions */
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#define RETENTION_ENTRY_TICKS_2 0x1
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#define RETENTION_ENTRY_TICKS_8 0x2
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#define RETENTION_ENTRY_TICKS_32 0x3
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#define RETENTION_ENTRY_TICKS_64 0x4
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#define RETENTION_ENTRY_TICKS_128 0x5
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#define RETENTION_ENTRY_TICKS_256 0x6
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#define RETENTION_ENTRY_TICKS_512 0x7
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/*******************************************************************************
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* CPU Extended Control register specific definitions.
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******************************************************************************/
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#define CPUECTLR_EL1 S3_1_C15_C2_1 /* Instruction def. */
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#define CPUECTLR_SMP_BIT (1 << 6)
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#define CPUECTLR_DIS_TWD_ACC_PFTCH_BIT (1 << 38)
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#define CPUECTLR_L2_IPFTCH_DIST_MASK (0x3 << 35)
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#define CPUECTLR_L2_DPFTCH_DIST_MASK (0x3 << 32)
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#define CPUECTLR_CPU_RET_CTRL_SHIFT 0
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#define CPUECTLR_CPU_RET_CTRL_MASK (0x7 << CPUECTLR_CPU_RET_CTRL_SHIFT)
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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#define CPUACTLR_EL1 S3_1_C15_C2_0 /* Instruction def. */
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#define CPUACTLR_DIS_OVERREAD (1 << 52)
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#define CPUACTLR_NO_ALLOC_WBWA (1 << 49)
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#define CPUACTLR_DCC_AS_DCCI (1 << 44)
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/*******************************************************************************
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* L2 Control register specific definitions.
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******************************************************************************/
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#define L2CTLR_EL1 S3_1_C11_C0_2 /* Instruction def. */
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#define L2CTLR_DATA_RAM_LATENCY_SHIFT 0
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#define L2CTLR_TAG_RAM_LATENCY_SHIFT 6
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#define L2_DATA_RAM_LATENCY_3_CYCLES 0x2
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#define L2_TAG_RAM_LATENCY_3_CYCLES 0x2
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/*******************************************************************************
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* L2 Extended Control register specific definitions.
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******************************************************************************/
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#define L2ECTLR_EL1 S3_1_C11_C0_3 /* Instruction def. */
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#define L2ECTLR_RET_CTRL_SHIFT 0
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#define L2ECTLR_RET_CTRL_MASK (0x7 << L2ECTLR_RET_CTRL_SHIFT)
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#endif /* __CORTEX_A57_H__ */
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