Sandrine Bailleux 54035fc467 Disable non-temporal hint on Cortex-A53/57 ... The LDNP/STNP instructions as implemented on Cortex-A53 and Cortex-A57 do not behave in a way most programmers expect, and will most probably result in a significant speed degradation to any code that employs them. The ARMv8-A architecture (see Document ARM DDI 0487A.h, section D3.4.3) allows cores to ignore the non-temporal hint and treat LDNP/STNP as LDP/STP instead. This patch introduces 2 new build flags: A53_DISABLE_NON_TEMPORAL_HINT and A57_DISABLE_NON_TEMPORAL_HINT to enforce this behaviour on Cortex-A53 and Cortex-A57. They are enabled by default. The string printed in debug builds when a specific CPU errata workaround is compiled in but skipped at runtime has been generalised, so that it can be reused for the non-temporal hint use case as well. Change-Id: I3e354f4797fd5d3959872a678e160322b13867a1		2016-02-08 09:31:18 +00:00
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aem_generic.h	Add CPU specific power management operations	2014-08-20 19:14:31 +01:00
cortex_a35.h	Add support for ARM Cortex-A35 processor	2016-01-12 09:25:12 +00:00
cortex_a53.h	Add macros for retention control in Cortex-A53/A57	2015-08-24 21:30:21 +05:30
cortex_a57.h	Disable non-temporal hint on Cortex-A53/57	2016-02-08 09:31:18 +00:00
cortex_a72.h	Juno R2: Configure the correct L2 RAM latency values	2015-11-19 14:53:58 +00:00
cpu_macros.S	Remove dashes from image names: 'BL3-x' --> 'BL3x'	2015-12-14 12:31:37 +00:00
denver.h	Add "Project Denver" CPU support	2015-07-24 09:08:27 +05:30