249 lines
7.1 KiB
ArmAsm
249 lines
7.1 KiB
ArmAsm
/*
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* Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <bl_common.h>
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#include <cortex_a53.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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/* ---------------------------------------------
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* Disable L1 data cache and unified L2 cache
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* ---------------------------------------------
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*/
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func cortex_a53_disable_dcache
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mrs x1, sctlr_el3
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bic x1, x1, #SCTLR_C_BIT
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msr sctlr_el3, x1
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isb
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ret
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endfunc cortex_a53_disable_dcache
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/* ---------------------------------------------
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* Disable intra-cluster coherency
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* ---------------------------------------------
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*/
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func cortex_a53_disable_smp
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mrs x0, CPUECTLR_EL1
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bic x0, x0, #CPUECTLR_SMP_BIT
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msr CPUECTLR_EL1, x0
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isb
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dsb sy
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ret
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endfunc cortex_a53_disable_smp
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/* --------------------------------------------------
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* Errata Workaround for Cortex A53 Errata #826319.
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* This applies only to revision <= r0p2 of Cortex A53.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Clobbers : x0 - x5
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* --------------------------------------------------
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*/
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func errata_a53_826319_wa
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/*
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* Compare x0 against revision r0p2
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*/
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cmp x0, #2
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b.ls apply_826319
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#if DEBUG
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b print_revision_warning
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#else
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ret
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#endif
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apply_826319:
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mrs x1, L2ACTLR_EL1
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bic x1, x1, #L2ACTLR_ENABLE_UNIQUECLEAN
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orr x1, x1, #L2ACTLR_DISABLE_CLEAN_PUSH
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msr L2ACTLR_EL1, x1
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ret
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endfunc errata_a53_826319_wa
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/* ---------------------------------------------------------------------
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* Disable the cache non-temporal hint.
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*
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* This ignores the Transient allocation hint in the MAIR and treats
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* allocations the same as non-transient allocation types. As a result,
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* the LDNP and STNP instructions in AArch64 behave the same as the
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* equivalent LDP and STP instructions.
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*
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* This is relevant only for revisions <= r0p3 of Cortex-A53.
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* From r0p4 and onwards, the bit to disable the hint is enabled by
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* default at reset.
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*
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Clobbers : x0 - x5
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* ---------------------------------------------------------------------
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*/
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func a53_disable_non_temporal_hint
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/*
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* Compare x0 against revision r0p3
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*/
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cmp x0, #3
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b.ls disable_hint
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#if DEBUG
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b print_revision_warning
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#else
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ret
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#endif
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disable_hint:
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mrs x1, CPUACTLR_EL1
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orr x1, x1, #CPUACTLR_DTAH
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msr CPUACTLR_EL1, x1
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ret
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endfunc a53_disable_non_temporal_hint
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/* -------------------------------------------------
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* The CPU Ops reset function for Cortex-A53.
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* Clobbers: x0-x5, x15, x19, x30
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* -------------------------------------------------
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*/
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func cortex_a53_reset_func
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mov x19, x30
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mrs x0, midr_el1
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/*
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* Extract the variant[20:23] and revision[0:3] from x0
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* and pack it in x15[0:7] as variant[4:7] and revision[0:3].
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* First extract x0[16:23] to x15[0:7] and zero fill the rest.
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* Then extract x0[0:3] into x15[0:3] retaining other bits.
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*/
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ubfx x15, x0, #(MIDR_VAR_SHIFT - MIDR_REV_BITS), \
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#(MIDR_REV_BITS + MIDR_VAR_BITS)
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bfxil x15, x0, #MIDR_REV_SHIFT, #MIDR_REV_BITS
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#if ERRATA_A53_826319
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mov x0, x15
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bl errata_a53_826319_wa
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#endif
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#if ERRATA_A53_836870 || A53_DISABLE_NON_TEMPORAL_HINT
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mov x0, x15
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bl a53_disable_non_temporal_hint
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#endif
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/* ---------------------------------------------
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* As a bare minimum enable the SMP bit if it is
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* not already set.
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* ---------------------------------------------
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*/
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mrs x0, CPUECTLR_EL1
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tst x0, #CPUECTLR_SMP_BIT
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b.ne skip_smp_setup
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orr x0, x0, #CPUECTLR_SMP_BIT
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msr CPUECTLR_EL1, x0
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skip_smp_setup:
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isb
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ret x19
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endfunc cortex_a53_reset_func
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func cortex_a53_core_pwr_dwn
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mov x18, x30
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/* ---------------------------------------------
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* Turn off caches.
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* ---------------------------------------------
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*/
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bl cortex_a53_disable_dcache
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/* ---------------------------------------------
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* Flush L1 caches.
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* ---------------------------------------------
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*/
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mov x0, #DCCISW
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bl dcsw_op_level1
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/* ---------------------------------------------
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* Come out of intra cluster coherency
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* ---------------------------------------------
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*/
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mov x30, x18
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b cortex_a53_disable_smp
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endfunc cortex_a53_core_pwr_dwn
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func cortex_a53_cluster_pwr_dwn
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mov x18, x30
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/* ---------------------------------------------
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* Turn off caches.
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* ---------------------------------------------
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*/
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bl cortex_a53_disable_dcache
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/* ---------------------------------------------
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* Flush L1 caches.
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* ---------------------------------------------
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*/
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mov x0, #DCCISW
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bl dcsw_op_level1
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/* ---------------------------------------------
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* Disable the optional ACP.
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* ---------------------------------------------
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*/
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bl plat_disable_acp
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/* ---------------------------------------------
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* Flush L2 caches.
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* ---------------------------------------------
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*/
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mov x0, #DCCISW
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bl dcsw_op_level2
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/* ---------------------------------------------
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* Come out of intra cluster coherency
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* ---------------------------------------------
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*/
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mov x30, x18
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b cortex_a53_disable_smp
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endfunc cortex_a53_cluster_pwr_dwn
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/* ---------------------------------------------
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* This function provides cortex_a53 specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.cortex_a53_regs, "aS"
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cortex_a53_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func cortex_a53_cpu_reg_dump
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adr x6, cortex_a53_regs
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mrs x8, CPUECTLR_EL1
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ret
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endfunc cortex_a53_cpu_reg_dump
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declare_cpu_ops cortex_a53, CORTEX_A53_MIDR
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