393 lines
10 KiB
C
393 lines
10 KiB
C
/*
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <assert.h>
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#include <stdbool.h>
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#include <string.h>
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#include <arch_helpers.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <context.h>
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#include <denver.h>
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#include <lib/el3_runtime/context_mgmt.h>
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#include <lib/psci/psci.h>
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#include <mce.h>
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#include <plat/common/platform.h>
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#include <se.h>
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#include <smmu.h>
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#include <t194_nvg.h>
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#include <tegra194_private.h>
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#include <tegra_platform.h>
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#include <tegra_private.h>
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extern void tegra194_cpu_reset_handler(void);
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extern uint32_t __tegra194_cpu_reset_handler_data,
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__tegra194_cpu_reset_handler_end;
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/* TZDRAM offset for saving SMMU context */
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#define TEGRA194_SMMU_CTX_OFFSET 16U
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/* state id mask */
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#define TEGRA194_STATE_ID_MASK 0xFU
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/* constants to get power state's wake time */
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#define TEGRA194_WAKE_TIME_MASK 0x0FFFFFF0U
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#define TEGRA194_WAKE_TIME_SHIFT 4U
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/* default core wake mask for CPU_SUSPEND */
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#define TEGRA194_CORE_WAKE_MASK 0x180cU
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static struct t19x_psci_percpu_data {
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uint32_t wake_time;
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} __aligned(CACHE_WRITEBACK_GRANULE) t19x_percpu_data[PLATFORM_CORE_COUNT];
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/*
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* tegra_fake_system_suspend acts as a boolean var controlling whether
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* we are going to take fake system suspend code or normal system suspend code
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* path. This variable is set inside the sip call handlers, when the kernel
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* requests an SIP call to set the suspend debug flags.
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*/
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bool tegra_fake_system_suspend;
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int32_t tegra_soc_validate_power_state(uint32_t power_state,
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psci_power_state_t *req_state)
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{
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uint8_t state_id = (uint8_t)psci_get_pstate_id(power_state) &
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TEGRA194_STATE_ID_MASK;
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uint32_t cpu = plat_my_core_pos();
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int32_t ret = PSCI_E_SUCCESS;
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/* save the core wake time (in TSC ticks)*/
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t19x_percpu_data[cpu].wake_time = (power_state & TEGRA194_WAKE_TIME_MASK)
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<< TEGRA194_WAKE_TIME_SHIFT;
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/*
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* Clean percpu_data[cpu] to DRAM. This needs to be done to ensure that
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* the correct value is read in tegra_soc_pwr_domain_suspend(), which
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* is called with caches disabled. It is possible to read a stale value
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* from DRAM in that function, because the L2 cache is not flushed
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* unless the cluster is entering CC6/CC7.
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*/
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clean_dcache_range((uint64_t)&t19x_percpu_data[cpu],
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sizeof(t19x_percpu_data[cpu]));
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/* Sanity check the requested state id */
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switch (state_id) {
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case PSTATE_ID_CORE_IDLE:
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case PSTATE_ID_CORE_POWERDN:
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/* Core powerdown request */
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req_state->pwr_domain_state[MPIDR_AFFLVL0] = state_id;
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req_state->pwr_domain_state[MPIDR_AFFLVL1] = state_id;
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break;
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default:
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ERROR("%s: unsupported state id (%d)\n", __func__, state_id);
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ret = PSCI_E_INVALID_PARAMS;
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break;
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}
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return ret;
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}
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int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
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{
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const plat_local_state_t *pwr_domain_state;
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uint8_t stateid_afflvl0, stateid_afflvl2;
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plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
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uint64_t smmu_ctx_base;
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uint32_t val;
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mce_cstate_info_t sc7_cstate_info = {
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.cluster = (uint32_t)TEGRA_NVG_CLUSTER_CC6,
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.system = (uint32_t)TEGRA_NVG_SYSTEM_SC7,
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.system_state_force = 1U,
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.update_wake_mask = 1U,
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};
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uint32_t cpu = plat_my_core_pos();
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int32_t ret = 0;
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/* get the state ID */
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pwr_domain_state = target_state->pwr_domain_state;
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stateid_afflvl0 = pwr_domain_state[MPIDR_AFFLVL0] &
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TEGRA194_STATE_ID_MASK;
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stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] &
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TEGRA194_STATE_ID_MASK;
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if ((stateid_afflvl0 == PSTATE_ID_CORE_IDLE) ||
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(stateid_afflvl0 == PSTATE_ID_CORE_POWERDN)) {
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/* Enter CPU idle/powerdown */
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val = (stateid_afflvl0 == PSTATE_ID_CORE_IDLE) ?
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(uint32_t)TEGRA_NVG_CORE_C6 : (uint32_t)TEGRA_NVG_CORE_C7;
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ret = mce_command_handler((uint64_t)MCE_CMD_ENTER_CSTATE, (uint64_t)val,
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percpu_data[cpu].wake_time, 0);
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assert(ret == 0);
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} else if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) {
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/* save 'Secure Boot' Processor Feature Config Register */
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val = mmio_read_32(TEGRA_MISC_BASE + MISCREG_PFCFG);
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mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_SECURE_BOOTP_FCFG, val);
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/* save SMMU context */
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smmu_ctx_base = params_from_bl2->tzdram_base +
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tegra194_get_smmu_ctx_offset();
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tegra_smmu_save_context((uintptr_t)smmu_ctx_base);
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/*
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* Suspend SE, RNG1 and PKA1 only on silcon and fpga,
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* since VDK does not support atomic se ctx save
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*/
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if (tegra_platform_is_silicon() || tegra_platform_is_fpga()) {
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ret = tegra_se_suspend();
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assert(ret == 0);
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}
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if (!tegra_fake_system_suspend) {
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/* Prepare for system suspend */
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mce_update_cstate_info(&sc7_cstate_info);
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do {
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val = (uint32_t)mce_command_handler(
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(uint32_t)MCE_CMD_IS_SC7_ALLOWED,
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(uint32_t)TEGRA_NVG_CORE_C7,
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MCE_CORE_SLEEP_TIME_INFINITE,
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0U);
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} while (val == 0U);
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/* Instruct the MCE to enter system suspend state */
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ret = mce_command_handler(
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(uint64_t)MCE_CMD_ENTER_CSTATE,
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(uint64_t)TEGRA_NVG_CORE_C7,
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MCE_CORE_SLEEP_TIME_INFINITE,
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0U);
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assert(ret == 0);
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/* set system suspend state for house-keeping */
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tegra194_set_system_suspend_entry();
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}
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} else {
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; /* do nothing */
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}
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return PSCI_E_SUCCESS;
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}
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/*******************************************************************************
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* Platform handler to calculate the proper target power level at the
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* specified affinity level
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******************************************************************************/
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plat_local_state_t tegra_soc_get_target_pwr_state(uint32_t lvl,
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const plat_local_state_t *states,
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uint32_t ncpu)
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{
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plat_local_state_t target = *states;
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int32_t cluster_powerdn = 1;
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uint32_t core_pos = (uint32_t)read_mpidr() & MPIDR_CPU_MASK;
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uint32_t num_cpus = ncpu, pos = 0;
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mce_cstate_info_t cstate_info = { 0 };
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/* get the current core's power state */
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target = states[core_pos];
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/* CPU suspend */
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if ((lvl == MPIDR_AFFLVL1) && (target == PSTATE_ID_CORE_POWERDN)) {
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/* Program default wake mask */
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cstate_info.wake_mask = TEGRA194_CORE_WAKE_MASK;
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cstate_info.update_wake_mask = 1;
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mce_update_cstate_info(&cstate_info);
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}
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/* CPU off */
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if ((lvl == MPIDR_AFFLVL1) && (target == PLAT_MAX_OFF_STATE)) {
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/* find out the number of ON cpus in the cluster */
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do {
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target = states[pos];
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if (target != PLAT_MAX_OFF_STATE) {
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cluster_powerdn = 0;
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}
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--num_cpus;
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pos++;
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} while (num_cpus != 0U);
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/* Enable cluster powerdn from last CPU in the cluster */
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if (cluster_powerdn != 0) {
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/* Enable CC6 */
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/* todo */
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/* If cluster group needs to be railgated, request CG7 */
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/* todo */
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/* Turn off wake mask */
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cstate_info.update_wake_mask = 1U;
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mce_update_cstate_info(&cstate_info);
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} else {
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/* Turn off wake_mask */
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cstate_info.update_wake_mask = 1U;
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mce_update_cstate_info(&cstate_info);
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}
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}
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/* System Suspend */
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if ((lvl == MPIDR_AFFLVL2) || (target == PSTATE_ID_SOC_POWERDN)) {
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return PSTATE_ID_SOC_POWERDN;
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}
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/* default state */
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return PSCI_LOCAL_STATE_RUN;
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}
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int32_t tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state)
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{
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const plat_local_state_t *pwr_domain_state =
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target_state->pwr_domain_state;
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plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
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uint8_t stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] &
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TEGRA194_STATE_ID_MASK;
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uint64_t val;
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u_register_t ns_sctlr_el1;
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if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) {
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/*
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* The TZRAM loses power when we enter system suspend. To
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* allow graceful exit from system suspend, we need to copy
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* BL3-1 over to TZDRAM.
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*/
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val = params_from_bl2->tzdram_base +
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tegra194_get_cpu_reset_handler_size();
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memcpy((void *)(uintptr_t)val, (void *)(uintptr_t)BL31_BASE,
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(uintptr_t)&__BL31_END__ - (uintptr_t)BL31_BASE);
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/*
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* In fake suspend mode, ensure that the loopback procedure
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* towards system suspend exit is started, instead of calling
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* WFI. This is done by disabling both MMU's of EL1 & El3
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* and calling tegra_secure_entrypoint().
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*/
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if (tegra_fake_system_suspend) {
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/*
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* Disable EL1's MMU.
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*/
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ns_sctlr_el1 = read_sctlr_el1();
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ns_sctlr_el1 &= (~((u_register_t)SCTLR_M_BIT));
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write_sctlr_el1(ns_sctlr_el1);
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/*
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* Disable MMU to power up the CPU in a "clean"
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* state
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*/
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disable_mmu_el3();
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tegra_secure_entrypoint();
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panic();
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}
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}
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return PSCI_E_SUCCESS;
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}
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int32_t tegra_soc_pwr_domain_on(u_register_t mpidr)
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{
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uint64_t target_cpu = mpidr & MPIDR_CPU_MASK;
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uint64_t target_cluster = (mpidr & MPIDR_CLUSTER_MASK) >>
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MPIDR_AFFINITY_BITS;
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int32_t ret = 0;
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if (target_cluster > ((uint32_t)PLATFORM_CLUSTER_COUNT - 1U)) {
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ERROR("%s: unsupported CPU (0x%lx)\n", __func__ , mpidr);
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return PSCI_E_NOT_PRESENT;
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}
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/* construct the target CPU # */
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target_cpu += (target_cluster << 1U);
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ret = mce_command_handler((uint64_t)MCE_CMD_ONLINE_CORE, target_cpu, 0U, 0U);
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if (ret < 0) {
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return PSCI_E_DENIED;
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}
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return PSCI_E_SUCCESS;
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}
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int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
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{
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uint8_t stateid_afflvl2 = target_state->pwr_domain_state[PLAT_MAX_PWR_LVL];
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/*
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* Reset power state info for CPUs when onlining, we set
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* deepest power when offlining a core but that may not be
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* requested by non-secure sw which controls idle states. It
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* will re-init this info from non-secure software when the
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* core come online.
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*/
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/*
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* Check if we are exiting from deep sleep and restore SE
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* context if we are.
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*/
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if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) {
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/* Init SMMU */
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tegra_smmu_init();
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/* Resume SE, RNG1 and PKA1 */
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tegra_se_resume();
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/*
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* Reset power state info for the last core doing SC7
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* entry and exit, we set deepest power state as CC7
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* and SC7 for SC7 entry which may not be requested by
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* non-secure SW which controls idle states.
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*/
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}
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return PSCI_E_SUCCESS;
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}
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int32_t tegra_soc_pwr_domain_off(const psci_power_state_t *target_state)
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{
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uint64_t impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK;
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int32_t ret = 0;
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(void)target_state;
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/* Disable Denver's DCO operations */
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if (impl == DENVER_IMPL) {
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denver_disable_dco();
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}
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/* Turn off CPU */
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ret = mce_command_handler((uint64_t)MCE_CMD_ENTER_CSTATE,
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(uint64_t)TEGRA_NVG_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, 0U);
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assert(ret == 0);
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return PSCI_E_SUCCESS;
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}
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__dead2 void tegra_soc_prepare_system_off(void)
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{
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/* System power off */
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/* SC8 */
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wfi();
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/* wait for the system to power down */
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for (;;) {
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;
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}
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}
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int32_t tegra_soc_prepare_system_reset(void)
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{
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return PSCI_E_SUCCESS;
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}
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