arm-trusted-firmware/include
Mikael Olsson 76a21174d2 Add SiP service to configure Arm Ethos-N NPU
By default the Arm Ethos-N NPU will boot up in secure mode. In this mode
the non-secure world cannot access the registers needed to use the NPU.
To still allow the non-secure world to use the NPU, a SiP service has
been added that can delegate non-secure access to the registers needed
to use it.

Only the HW_CONFIG for the Arm Juno platform has been updated to include
the device tree for the NPU and the platform currently only loads the
HW_CONFIG in AArch64 builds.

Signed-off-by: Mikael Olsson <mikael.olsson@arm.com>
Change-Id: I65dfd864042ed43faae0a259dcf319cbadb5f3d2
2021-04-20 15:42:18 +02:00
..
arch Merge changes from topic "dcc_console" into integration 2021-04-13 21:42:55 +02:00
bl1 Specify signed-ness of constants 2020-08-14 11:36:05 +00:00
bl2 BL2_AT_EL3: Enable pointer authentication support 2019-02-27 11:58:09 +00:00
bl2u Standardise header guards across codebase 2018-11-08 10:20:19 +00:00
bl31 Use correct type when reading SCR register 2020-01-28 11:10:48 +00:00
bl32 spd: tlkd: support new TLK SMCs for RPMB service 2020-03-21 19:00:05 -07:00
common tbbr-cot: conditional definition for the macro 2021-03-24 09:49:31 +05:30
drivers Add SiP service to configure Arm Ethos-N NPU 2021-04-20 15:42:18 +02:00
dt-bindings fdts: stm32mp1: realign device tree with kernel 2020-09-24 09:07:57 +02:00
export Increase type widths to satisfy width requirements 2020-10-12 10:55:03 -05:00
lib Merge "Fix: Remove save/restore of EL2 timer registers" into integration 2021-04-07 21:25:26 +02:00
plat Add SiP service to configure Arm Ethos-N NPU 2021-04-20 15:42:18 +02:00
services FF-A: implement FFA_SECONDARY_EP_REGISTER 2021-03-15 12:29:11 +01:00
tools_share tools: add mechanism to allow platform specific image UUID 2021-03-24 09:49:31 +05:30