David Cunado 495f3d3c51 Reset debug registers MDCR-EL3/SDCR and MDCR_EL2/HDCR ... In order to avoid unexpected traps into EL3/MON mode, this patch resets the debug registers, MDCR_EL3 and MDCR_EL2 for AArch64, and SDCR and HDCR for AArch32. MDCR_EL3/SDCR is zero'ed when EL3/MON mode is entered, at the start of BL1 and BL31/SMP_MIN. For MDCR_EL2/HDCR, this patch zero's the bits that are architecturally UNKNOWN values on reset. This is done when exiting from EL3/MON mode but only on platforms that support EL2/HYP mode but choose to exit to EL1/SVC mode. Fixes ARM-software/tf-issues#430 Change-Id: Idb992232163c072faa08892251b5626ae4c3a5b6 Signed-off-by: David Cunado <david.cunado@arm.com>		2016-11-09 15:45:06 +00:00
..
bl1	FWU: Add Generic Firmware Update framework support in BL1	2015-12-09 17:41:18 +00:00
bl31	Introduce PSCI Library Interface	2016-07-19 10:19:01 +01:00
bl32	AArch32: Support in SP_MIN to receive arguments from BL2	2016-09-21 16:28:46 +01:00
common	Reset debug registers MDCR-EL3/SDCR and MDCR_EL2/HDCR	2016-11-09 15:45:06 +00:00
drivers	partition: check GPT partition table	2016-09-20 13:19:32 +08:00
lib	Reset debug registers MDCR-EL3/SDCR and MDCR_EL2/HDCR	2016-11-09 15:45:06 +00:00
plat	Introduce ARM SiP service	2016-10-12 15:36:45 +01:00
services	PSCI: Do psci_setup() as part of std_svc_setup()	2016-09-22 17:07:20 +01:00