Sieu Mun Tang 692541051b feat(intel): support ECDSA HASH Signing ... Supporting the command to send digital signature signing request on a data blob. This include ECC algorithm such as NISP P-256, NISP P-384, Brainpool 256 and, Branpool 384 Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com> Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com> Change-Id: I12cf0f1ceaf07c33a110eae398d3ad82a9b13d38		2022-05-11 16:57:29 +08:00
..
plat_macros.S	intel: Platform common code refactor	2019-08-07 12:19:11 +00:00
platform_def.h	feat(intel): implement timer init divider via cpu frequency. (#1)	2022-05-06 17:37:45 +02:00
socfpga_emac.h	intel: Enable EMAC PHY in Intel FPGA platform	2020-02-25 10:19:51 +08:00
socfpga_f2sdram_manager.h	feat(intel): add support for F2S and S2F bridge SMC with mask to enable, disable and reset bridge	2022-05-05 22:58:03 +08:00
socfpga_fcs.h	feat(intel): support ECDSA HASH Signing	2022-05-11 16:57:29 +08:00
socfpga_handoff.h	intel: Change boot source selection	2020-02-03 14:31:52 +08:00
socfpga_mailbox.h	feat(intel): support ECDSA HASH Signing	2022-05-11 16:57:29 +08:00
socfpga_noc.h	feat(intel): enable firewall for OCRAM in BL31	2022-04-28 19:08:35 +08:00
socfpga_private.h	feat(intel): implement timer init divider via cpu frequency. (#1)	2022-05-06 17:37:45 +02:00
socfpga_reset_manager.h	feat(intel): add support for F2S and S2F bridge SMC with mask to enable, disable and reset bridge	2022-05-05 22:58:03 +08:00
socfpga_sip_svc.h	feat(intel): support ECDSA HASH Signing	2022-05-11 16:57:29 +08:00
socfpga_system_manager.h	feat(intel): add support for F2S and S2F bridge SMC with mask to enable, disable and reset bridge	2022-05-05 22:58:03 +08:00