arm-trusted-firmware/plat/renesas/rcar
Anthony Steinhauser f461fe346b Prevent speculative execution past ERET
Even though ERET always causes a jump to another address, aarch64 CPUs
speculatively execute following instructions as if the ERET
instruction was not a jump instruction.
The speculative execution does not cross privilege-levels (to the jump
target as one would expect), but it continues on the kernel privilege
level as if the ERET instruction did not change the control flow -
thus execution anything that is accidentally linked after the ERET
instruction. Later, the results of this speculative execution are
always architecturally discarded, however they can leak data using
microarchitectural side channels. This speculative execution is very
reliable (seems to be unconditional) and it manages to complete even
relatively performance-heavy operations (e.g. multiple dependent
fetches from uncached memory).

This was fixed in Linux, FreeBSD, OpenBSD and Optee OS:
679db70801
29fb48ace4
3a08873ece
abfd092aa1

It is demonstrated in a SafeSide example:
https://github.com/google/safeside/blob/master/demos/eret_hvc_smc_wrapper.cc
https://github.com/google/safeside/blob/master/kernel_modules/kmod_eret_hvc_smc/eret_hvc_smc_module.c

Signed-off-by: Anthony Steinhauser <asteinhauser@google.com>
Change-Id: Iead39b0b9fb4b8d8b5609daaa8be81497ba63a0f
2020-01-22 21:42:51 +00:00
..
aarch64 Prevent speculative execution past ERET 2020-01-22 21:42:51 +00:00
include rcar_get3: drivers: ddr: Partly unify register macros between DDR A and B 2019-08-29 13:02:30 +02:00
bl2_cpg_init.c rcar_gen3: plat: Rename RCAR_PRODUCT_* to PRR_PRODUCT_* 2019-08-16 15:15:12 +02:00
bl2_interrupt_error.c rcar_gen3: plat: Dump EL3 interrupt error registers 2019-01-08 14:08:44 +01:00
bl2_plat_mem_params_desc.c rcar_gen3: plat: Pass DT to OpTee OS 2020-01-06 03:07:35 +01:00
bl2_plat_setup.c rcar_gen3: Add missing #{address,size}-cells into generated DT 2020-01-15 05:18:03 +01:00
bl2_secure_setting.c rcar_gen3: plat: Add initial D3 support 2019-04-02 03:40:51 +02:00
bl31_plat_setup.c rcar_gen3: plat: Rename RCAR_PRODUCT_* to PRR_PRODUCT_* 2019-08-16 15:15:12 +02:00
plat_image_load.c Sanitise includes across codebase 2019-01-04 10:43:17 +00:00
plat_pm.c rcar_gen3: drivers: Change to restore timer counter value at resume 2019-04-11 12:57:03 +02:00
plat_storage.c Sanitise includes across codebase 2019-01-04 10:43:17 +00:00
plat_topology.c Sanitise includes across codebase 2019-01-04 10:43:17 +00:00
platform.mk rcar_gen3: drivers: ddr: Move DDR drivers out of staging 2020-01-06 03:07:35 +01:00
rcar_common.c Update renesas platform to not rely on undefined overflow behaviour 2019-07-11 12:10:58 +01:00