Alexei Fedorov e290a8fcbc AArch64: Disable Secure Cycle Counter ... This patch fixes an issue when secure world timing information can be leaked because Secure Cycle Counter is not disabled. For ARMv8.5 the counter gets disabled by setting MDCR_El3.SCCD bit on CPU cold/warm boot. For the earlier architectures PMCR_EL0 register is saved/restored on secure world entry/exit from/to Non-secure state, and cycle counting gets disabled by setting PMCR_EL0.DP bit. 'include\aarch64\arch.h' header file was tided up and new ARMv8.5-PMU related definitions were added. Change-Id: I6f56db6bc77504634a352388990ad925a69ebbfa Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>		2019-08-21 15:43:24 +01:00
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bl1_arch_setup.c	bl1: include bl1_private.h in aarch* files	2017-06-23 09:38:06 +02:00
bl1_context_mgmt.c	Refactor SPSR initialisation code	2019-07-24 12:49:54 +01:00
bl1_entrypoint.S	BL1: Enable pointer authentication support	2019-02-27 11:58:09 +00:00
bl1_exceptions.S	AArch64: Disable Secure Cycle Counter	2019-08-21 15:43:24 +01:00