6bc243825f
aarch32 CPUs speculatively execute instructions following a ERET as if it was not a jump instruction. This could lead to cache-based side channel vulnerabilities. The software fix is to place barrier instructions following ERET. The counterpart patch for aarch64 is merged: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=f461fe346b728d0e88142fd7b8f2816415af18bc Change-Id: I2aa3105bee0b92238f389830b3a3b8650f33af3d Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
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arch.h | ||
arch_features.h | ||
arch_helpers.h | ||
asm_macros.S | ||
assert_macros.S | ||
console_macros.S | ||
el3_common_macros.S | ||
smccc_helpers.h | ||
smccc_macros.S |