77612b90ac
This patch adds necessary barriers after GPT entries are modified so that the writes are observed correctly by the GPC hardware. The shareability of GPC fetches are changed from OSH to ISH so that they align with the shareability of MMU attributes for the region. Thus by adding a dsbishst() between the GPT L1 entry write as part of granule migration at runtime, we can now remove the clean cache maintenance operation (CMO) for that region. Signed-off-by: Soby Mathew <soby.mathew@arm.com> Signed-off-by: Robert Wakim <robert.wakim@arm.com> Change-Id: Ib9e405b106f0db95c7fbdb26773c0ed41663a5b4 |
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readme.rst
Trusted Firmware-A
Trusted Firmware-A (TF-A) is a reference implementation of secure world software for Arm A-Profile architectures (Armv8-A and Armv7-A), including an Exception Level 3 (EL3) Secure Monitor. It provides a suitable starting point for productization of secure world boot and runtime firmware, in either the AArch32 or AArch64 execution states.
TF-A implements Arm interface standards, including:
- Power State Coordination Interface (PSCI)
- Trusted Board Boot Requirements CLIENT (TBBR-CLIENT)
- SMC Calling Convention
- System Control and Management Interface (SCMI)
- Software Delegated Exception Interface (SDEI)
The code is designed to be portable and reusable across hardware platforms and software models that are based on the Armv8-A and Armv7-A architectures.
In collaboration with interested parties, we will continue to enhance TF-A with reference implementations of Arm standards to benefit developers working with Armv7-A and Armv8-A TrustZone technology.
Users are encouraged to do their own security validation, including penetration testing, on any secure world code derived from TF-A.
More Info and Documentation
To find out more about Trusted Firmware-A, please view the full documentation that is available through trustedfirmware.org.
Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.