627 lines
16 KiB
C
627 lines
16 KiB
C
/*
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* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <desc_image_load.h>
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#include <arch_helpers.h>
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#include <bl_common.h>
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#include <bl1.h>
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#include <console.h>
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#include <debug.h>
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#include <mmio.h>
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#include <platform.h>
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#include <platform_def.h>
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#include <string.h>
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#include "avs_driver.h"
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#include "boot_init_dram.h"
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#include "cpg_registers.h"
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#include "board.h"
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#include "emmc_def.h"
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#include "emmc_hal.h"
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#include "emmc_std.h"
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#if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR
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#include "iic_dvfs.h"
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#endif
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#include "io_common.h"
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#include "qos_init.h"
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#include "rcar_def.h"
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#include "rcar_private.h"
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#include "rcar_version.h"
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#include "rom_api.h"
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IMPORT_SYM(unsigned long, __RO_START__, BL2_RO_BASE)
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IMPORT_SYM(unsigned long, __RO_END__, BL2_RO_LIMIT)
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#if USE_COHERENT_MEM
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IMPORT_SYM(unsigned long, __COHERENT_RAM_START__, BL2_COHERENT_RAM_BASE)
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IMPORT_SYM(unsigned long, __COHERENT_RAM_END__, BL2_COHERENT_RAM_LIMIT)
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#endif
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extern void plat_rcar_gic_driver_init(void);
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extern void plat_rcar_gic_init(void);
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extern void bl2_enter_bl31(const struct entry_point_info *bl_ep_info);
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extern void bl2_system_cpg_init(void);
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extern void bl2_secure_setting(void);
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extern void bl2_cpg_init(void);
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extern void rcar_io_emmc_setup(void);
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extern void rcar_io_setup(void);
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extern void rcar_swdt_release(void);
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extern void rcar_swdt_init(void);
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extern void rcar_rpc_init(void);
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extern void rcar_pfc_init(void);
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extern void rcar_dma_init(void);
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/* R-Car Gen3 product check */
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#if (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N)
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#define TARGET_PRODUCT RCAR_PRODUCT_H3
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#define TARGET_NAME "R-Car H3"
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#elif RCAR_LSI == RCAR_M3
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#define TARGET_PRODUCT RCAR_PRODUCT_M3
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#define TARGET_NAME "R-Car M3"
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#elif RCAR_LSI == RCAR_M3N
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#define TARGET_PRODUCT RCAR_PRODUCT_M3N
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#define TARGET_NAME "R-Car M3N"
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#elif RCAR_LSI == RCAR_E3
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#define TARGET_PRODUCT RCAR_PRODUCT_E3
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#define TARGET_NAME "R-Car E3"
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#endif
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#if (RCAR_LSI == RCAR_E3)
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#define GPIO_INDT (GPIO_INDT6)
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#define GPIO_BKUP_TRG_SHIFT ((uint32_t)1U<<13U)
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#else
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#define GPIO_INDT (GPIO_INDT1)
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#define GPIO_BKUP_TRG_SHIFT ((uint32_t)1U<<8U)
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#endif
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CASSERT((PARAMS_BASE + sizeof(bl2_to_bl31_params_mem_t) + 0x100)
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< (RCAR_SHARED_MEM_BASE + RCAR_SHARED_MEM_SIZE),
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assert_bl31_params_do_not_fit_in_shared_memory);
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static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
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#if (RCAR_LOSSY_ENABLE == 1)
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typedef struct bl2_lossy_info {
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uint32_t magic;
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uint32_t a0;
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uint32_t b0;
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} bl2_lossy_info_t;
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static void bl2_lossy_setting(uint32_t no, uint64_t start_addr,
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uint64_t end_addr, uint32_t format,
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uint32_t enable)
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{
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bl2_lossy_info_t info;
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uint32_t reg;
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reg = format | (start_addr >> 20);
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mmio_write_32(AXI_DCMPAREACRA0 + 0x8 * no, reg);
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mmio_write_32(AXI_DCMPAREACRB0 + 0x8 * no, end_addr >> 20);
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mmio_write_32(AXI_DCMPAREACRA0 + 0x8 * no, reg | enable);
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info.magic = 0x12345678U;
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info.a0 = mmio_read_32(AXI_DCMPAREACRA0 + 0x8 * no);
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info.b0 = mmio_read_32(AXI_DCMPAREACRB0 + 0x8 * no);
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mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no, info.magic);
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mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no + 0x4, info.a0);
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mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no + 0x8, info.b0);
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NOTICE(" Entry %d: DCMPAREACRAx:0x%x DCMPAREACRBx:0x%x\n", no,
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mmio_read_32(AXI_DCMPAREACRA0 + 0x8 * no),
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mmio_read_32(AXI_DCMPAREACRB0 + 0x8 * no));
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}
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#endif
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void bl2_plat_flush_bl31_params(void)
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{
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uint32_t product_cut, product, cut;
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uint32_t boot_dev, boot_cpu;
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uint32_t lcs, reg, val;
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reg = mmio_read_32(RCAR_MODEMR);
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boot_dev = reg & MODEMR_BOOT_DEV_MASK;
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if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 ||
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boot_dev == MODEMR_BOOT_DEV_EMMC_50X8)
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emmc_terminate();
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if ((reg & MODEMR_BOOT_CPU_MASK) != MODEMR_BOOT_CPU_CR7)
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bl2_secure_setting();
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reg = mmio_read_32(RCAR_PRR);
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product_cut = reg & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK);
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product = reg & RCAR_PRODUCT_MASK;
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cut = reg & RCAR_CUT_MASK;
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if (product == RCAR_PRODUCT_M3)
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goto tlb;
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if (product == RCAR_PRODUCT_H3 && RCAR_CUT_VER20 > cut)
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goto tlb;
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/* Disable MFIS write protection */
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mmio_write_32(MFISWPCNTR, MFISWPCNTR_PASSWORD | 1);
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tlb:
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reg = mmio_read_32(RCAR_MODEMR);
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boot_cpu = reg & MODEMR_BOOT_CPU_MASK;
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if (boot_cpu != MODEMR_BOOT_CPU_CA57 &&
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boot_cpu != MODEMR_BOOT_CPU_CA53)
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goto mmu;
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if (product_cut == RCAR_PRODUCT_H3_CUT20) {
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mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE);
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mmio_write_32(IPMMUVI1_IMSCTLR, IMSCTLR_DISCACHE);
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mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE);
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mmio_write_32(IPMMUPV1_IMSCTLR, IMSCTLR_DISCACHE);
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mmio_write_32(IPMMUPV2_IMSCTLR, IMSCTLR_DISCACHE);
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mmio_write_32(IPMMUPV3_IMSCTLR, IMSCTLR_DISCACHE);
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} else if (product_cut == (RCAR_PRODUCT_M3N | RCAR_CUT_VER10) ||
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product_cut == (RCAR_PRODUCT_M3N | RCAR_CUT_VER11)) {
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mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE);
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mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE);
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} else if (product_cut == (RCAR_PRODUCT_E3 | RCAR_CUT_VER10)) {
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mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE);
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mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE);
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}
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if (product_cut == (RCAR_PRODUCT_H3_CUT20) ||
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product_cut == (RCAR_PRODUCT_M3N | RCAR_CUT_VER10) ||
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product_cut == (RCAR_PRODUCT_M3N | RCAR_CUT_VER11) ||
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product_cut == (RCAR_PRODUCT_E3 | RCAR_CUT_VER10)) {
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mmio_write_32(IPMMUHC_IMSCTLR, IMSCTLR_DISCACHE);
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mmio_write_32(IPMMURT_IMSCTLR, IMSCTLR_DISCACHE);
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mmio_write_32(IPMMUMP_IMSCTLR, IMSCTLR_DISCACHE);
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mmio_write_32(IPMMUDS0_IMSCTLR, IMSCTLR_DISCACHE);
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mmio_write_32(IPMMUDS1_IMSCTLR, IMSCTLR_DISCACHE);
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}
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mmu:
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mmio_write_32(IPMMUMM_IMSCTLR, IPMMUMM_IMSCTLR_ENABLE);
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mmio_write_32(IPMMUMM_IMAUXCTLR, IPMMUMM_IMAUXCTLR_NMERGE40_BIT);
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val = rcar_rom_get_lcs(&lcs);
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if (val) {
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ERROR("BL2: Failed to get the LCS. (%d)\n", val);
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panic();
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}
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if (lcs == LCS_SE)
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mmio_clrbits_32(P_ARMREG_SEC_CTRL, P_ARMREG_SEC_CTRL_PROT);
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rcar_swdt_release();
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bl2_system_cpg_init();
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#if RCAR_BL2_DCACHE == 1
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/* Disable data cache (clean and invalidate) */
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disable_mmu_el3();
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#endif
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}
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static uint32_t is_ddr_backup_mode(void)
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{
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#if RCAR_SYSTEM_SUSPEND
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static uint32_t reason = RCAR_COLD_BOOT;
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static uint32_t once;
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#if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR
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uint8_t data;
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#endif
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if (once)
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return reason;
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once = 1;
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if ((mmio_read_32(GPIO_INDT) & GPIO_BKUP_TRG_SHIFT) == 0)
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return reason;
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#if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR
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if (rcar_iic_dvfs_receive(PMIC, REG_KEEP10, &data)) {
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ERROR("BL2: REG Keep10 READ ERROR.\n");
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panic();
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}
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if (KEEP10_MAGIC != data)
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reason = RCAR_WARM_BOOT;
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#else
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reason = RCAR_WARM_BOOT;
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#endif
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return reason;
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#else
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return RCAR_COLD_BOOT;
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#endif
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}
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int bl2_plat_handle_pre_image_load(unsigned int image_id)
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{
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u_register_t *boot_kind = (void *) BOOT_KIND_BASE;
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bl_mem_params_node_t *bl_mem_params;
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if (image_id != BL31_IMAGE_ID)
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return 0;
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bl_mem_params = get_bl_mem_params_node(image_id);
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if (is_ddr_backup_mode() == RCAR_COLD_BOOT)
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goto cold_boot;
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*boot_kind = RCAR_WARM_BOOT;
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flush_dcache_range(BOOT_KIND_BASE, sizeof(*boot_kind));
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console_flush();
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bl2_plat_flush_bl31_params();
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/* will not return */
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bl2_enter_bl31(&bl_mem_params->ep_info);
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cold_boot:
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*boot_kind = RCAR_COLD_BOOT;
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flush_dcache_range(BOOT_KIND_BASE, sizeof(*boot_kind));
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return 0;
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}
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int bl2_plat_handle_post_image_load(unsigned int image_id)
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{
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static bl2_to_bl31_params_mem_t *params;
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bl_mem_params_node_t *bl_mem_params;
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if (!params) {
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params = (bl2_to_bl31_params_mem_t *) PARAMS_BASE;
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memset((void *)PARAMS_BASE, 0, sizeof(*params));
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}
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bl_mem_params = get_bl_mem_params_node(image_id);
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switch (image_id) {
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case BL31_IMAGE_ID:
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break;
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case BL32_IMAGE_ID:
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memcpy(¶ms->bl32_ep_info, &bl_mem_params->ep_info,
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sizeof(entry_point_info_t));
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break;
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case BL33_IMAGE_ID:
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memcpy(¶ms->bl33_ep_info, &bl_mem_params->ep_info,
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sizeof(entry_point_info_t));
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break;
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}
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return 0;
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}
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meminfo_t *bl2_plat_sec_mem_layout(void)
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{
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return &bl2_tzram_layout;
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}
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void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
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u_register_t arg3, u_register_t arg4)
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{
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uint32_t reg, midr, lcs, boot_dev, boot_cpu, sscg, type, rev;
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uint32_t cut, product, product_cut, major, minor;
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int32_t ret;
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const char *str;
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const char *unknown = "unknown";
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const char *cpu_ca57 = "CA57";
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const char *cpu_ca53 = "CA53";
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const char *product_m3n = "M3N";
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const char *product_h3 = "H3";
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const char *product_m3 = "M3";
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const char *product_e3 = "E3";
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const char *lcs_secure = "SE";
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const char *lcs_cm = "CM";
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const char *lcs_dm = "DM";
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const char *lcs_sd = "SD";
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const char *lcs_fa = "FA";
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const char *sscg_off = "PLL1 nonSSCG Clock select";
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const char *sscg_on = "PLL1 SSCG Clock select";
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const char *boot_hyper80 = "HyperFlash(80MHz)";
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const char *boot_qspi40 = "QSPI Flash(40MHz)";
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const char *boot_qspi80 = "QSPI Flash(80MHz)";
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const char *boot_emmc25x1 = "eMMC(25MHz x1)";
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const char *boot_emmc50x8 = "eMMC(50MHz x8)";
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#if RCAR_LSI == RCAR_E3
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const char *boot_hyper160 = "HyperFlash(150MHz)";
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#else
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const char *boot_hyper160 = "HyperFlash(160MHz)";
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#endif
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reg = mmio_read_32(RCAR_MODEMR);
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boot_dev = reg & MODEMR_BOOT_DEV_MASK;
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boot_cpu = reg & MODEMR_BOOT_CPU_MASK;
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bl2_cpg_init();
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if (boot_cpu == MODEMR_BOOT_CPU_CA57 ||
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boot_cpu == MODEMR_BOOT_CPU_CA53) {
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rcar_pfc_init();
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/* console configuration (platform specific) done in driver */
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console_init(0, 0, 0);
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}
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plat_rcar_gic_driver_init();
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plat_rcar_gic_init();
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rcar_swdt_init();
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/* FIQ interrupts are taken to EL3 */
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write_scr_el3(read_scr_el3() | SCR_FIQ_BIT);
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write_daifclr(DAIF_FIQ_BIT);
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reg = read_midr();
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midr = reg & (MIDR_PN_MASK << MIDR_PN_SHIFT);
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switch (midr) {
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case MIDR_CA57:
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str = cpu_ca57;
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break;
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case MIDR_CA53:
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str = cpu_ca53;
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break;
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default:
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str = unknown;
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break;
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}
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NOTICE("BL2: R-Car Gen3 Initial Program Loader(%s) Rev.%s\n", str,
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version_of_renesas);
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reg = mmio_read_32(RCAR_PRR);
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product_cut = reg & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK);
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product = reg & RCAR_PRODUCT_MASK;
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cut = reg & RCAR_CUT_MASK;
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switch (product) {
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case RCAR_PRODUCT_H3:
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str = product_h3;
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break;
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case RCAR_PRODUCT_M3:
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str = product_m3;
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break;
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case RCAR_PRODUCT_M3N:
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str = product_m3n;
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break;
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case RCAR_PRODUCT_E3:
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str = product_e3;
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break;
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default:
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str = unknown;
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break;
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}
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if (RCAR_PRODUCT_M3_CUT11 == product_cut) {
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NOTICE("BL2: PRR is R-Car %s Ver.1.1 / Ver.1.2\n", str);
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} else {
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major = (reg & RCAR_MAJOR_MASK) >> RCAR_MAJOR_SHIFT;
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major = major + RCAR_MAJOR_OFFSET;
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minor = reg & RCAR_MINOR_MASK;
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NOTICE("BL2: PRR is R-Car %s Ver.%d.%d\n", str, major, minor);
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}
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if (product == RCAR_PRODUCT_E3) {
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reg = mmio_read_32(RCAR_MODEMR);
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sscg = reg & RCAR_SSCG_MASK;
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str = sscg == RCAR_SSCG_ENABLE ? sscg_on : sscg_off;
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NOTICE("BL2: %s\n", str);
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}
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rcar_get_board_type(&type, &rev);
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switch (type) {
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case BOARD_SALVATOR_X:
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case BOARD_KRIEK:
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case BOARD_STARTER_KIT:
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case BOARD_SALVATOR_XS:
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case BOARD_EBISU:
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case BOARD_STARTER_KIT_PRE:
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case BOARD_EBISU_4D:
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break;
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default:
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type = BOARD_UNKNOWN;
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break;
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}
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if (type == BOARD_UNKNOWN || rev == BOARD_REV_UNKNOWN)
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NOTICE("BL2: Board is %s Rev.---\n", GET_BOARD_NAME(type));
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else {
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NOTICE("BL2: Board is %s Rev.%d.%d\n",
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GET_BOARD_NAME(type),
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GET_BOARD_MAJOR(rev), GET_BOARD_MINOR(rev));
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}
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#if RCAR_LSI != RCAR_AUTO
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if (product != TARGET_PRODUCT) {
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ERROR("BL2: IPL was been built for the %s.\n", TARGET_NAME);
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ERROR("BL2: Please write the correct IPL to flash memory.\n");
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panic();
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}
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#endif
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rcar_avs_init();
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rcar_avs_setting();
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switch (boot_dev) {
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case MODEMR_BOOT_DEV_HYPERFLASH160:
|
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str = boot_hyper160;
|
|
break;
|
|
case MODEMR_BOOT_DEV_HYPERFLASH80:
|
|
str = boot_hyper80;
|
|
break;
|
|
case MODEMR_BOOT_DEV_QSPI_FLASH40:
|
|
str = boot_qspi40;
|
|
break;
|
|
case MODEMR_BOOT_DEV_QSPI_FLASH80:
|
|
str = boot_qspi80;
|
|
break;
|
|
case MODEMR_BOOT_DEV_EMMC_25X1:
|
|
str = boot_emmc25x1;
|
|
break;
|
|
case MODEMR_BOOT_DEV_EMMC_50X8:
|
|
str = boot_emmc50x8;
|
|
break;
|
|
default:
|
|
str = unknown;
|
|
break;
|
|
}
|
|
NOTICE("BL2: Boot device is %s\n", str);
|
|
|
|
rcar_avs_setting();
|
|
reg = rcar_rom_get_lcs(&lcs);
|
|
if (reg) {
|
|
str = unknown;
|
|
goto lcm_state;
|
|
}
|
|
|
|
switch (lcs) {
|
|
case LCS_CM:
|
|
str = lcs_cm;
|
|
break;
|
|
case LCS_DM:
|
|
str = lcs_dm;
|
|
break;
|
|
case LCS_SD:
|
|
str = lcs_sd;
|
|
break;
|
|
case LCS_SE:
|
|
str = lcs_secure;
|
|
break;
|
|
case LCS_FA:
|
|
str = lcs_fa;
|
|
break;
|
|
default:
|
|
str = unknown;
|
|
break;
|
|
}
|
|
|
|
lcm_state:
|
|
NOTICE("BL2: LCM state is %s\n", str);
|
|
|
|
rcar_avs_end();
|
|
is_ddr_backup_mode();
|
|
|
|
bl2_tzram_layout.total_base = BL31_BASE;
|
|
bl2_tzram_layout.total_size = BL31_LIMIT - BL31_BASE;
|
|
|
|
if (product == RCAR_PRODUCT_H3 && cut >= RCAR_CUT_VER30) {
|
|
#if (RCAR_DRAM_LPDDR4_MEMCONF == 0)
|
|
NOTICE("BL2: CH0: 0x400000000 - 0x440000000, 1 GiB\n");
|
|
NOTICE("BL2: CH1: 0x500000000 - 0x540000000, 1 GiB\n");
|
|
NOTICE("BL2: CH2: 0x600000000 - 0x640000000, 1 GiB\n");
|
|
NOTICE("BL2: CH3: 0x700000000 - 0x740000000, 1 GiB\n");
|
|
#elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && \
|
|
(RCAR_DRAM_CHANNEL == 5) && \
|
|
(RCAR_DRAM_SPLIT == 2)
|
|
NOTICE("BL2: CH0: 0x400000000 - 0x480000000, 2 GiB\n");
|
|
NOTICE("BL2: CH1: 0x500000000 - 0x580000000, 2 GiB\n");
|
|
#elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && (RCAR_DRAM_CHANNEL == 15)
|
|
NOTICE("BL2: CH0: 0x400000000 - 0x480000000, 2 GiB\n");
|
|
NOTICE("BL2: CH1: 0x500000000 - 0x580000000, 2 GiB\n");
|
|
NOTICE("BL2: CH2: 0x600000000 - 0x680000000, 2 GiB\n");
|
|
NOTICE("BL2: CH3: 0x700000000 - 0x780000000, 2 GiB\n");
|
|
#endif
|
|
}
|
|
|
|
if (product == RCAR_PRODUCT_E3) {
|
|
#if (RCAR_DRAM_DDR3L_MEMCONF == 0)
|
|
NOTICE("BL2: 0x400000000 - 0x440000000, 1 GiB\n");
|
|
#elif (RCAR_DRAM_DDR3L_MEMCONF == 1)
|
|
NOTICE("BL2: 0x400000000 - 0x480000000, 2 GiB\n");
|
|
#endif
|
|
}
|
|
|
|
if (boot_cpu == MODEMR_BOOT_CPU_CA57 ||
|
|
boot_cpu == MODEMR_BOOT_CPU_CA53) {
|
|
ret = rcar_dram_init();
|
|
if (ret) {
|
|
NOTICE("BL2: Failed to DRAM initialize (%d).\n", ret);
|
|
panic();
|
|
}
|
|
rcar_qos_init();
|
|
}
|
|
|
|
if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 ||
|
|
boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) {
|
|
if (rcar_emmc_init() != EMMC_SUCCESS) {
|
|
NOTICE("BL2: Failed to eMMC driver initialize.\n");
|
|
panic();
|
|
}
|
|
rcar_emmc_memcard_power(EMMC_POWER_ON);
|
|
if (rcar_emmc_mount() != EMMC_SUCCESS) {
|
|
NOTICE("BL2: Failed to eMMC mount operation.\n");
|
|
panic();
|
|
}
|
|
} else {
|
|
rcar_rpc_init();
|
|
rcar_dma_init();
|
|
}
|
|
|
|
reg = mmio_read_32(RST_WDTRSTCR);
|
|
reg &= ~WDTRSTCR_RWDT_RSTMSK;
|
|
reg |= WDTRSTCR_PASSWORD;
|
|
mmio_write_32(RST_WDTRSTCR, reg);
|
|
|
|
mmio_write_32(CPG_CPGWPR, CPGWPR_PASSWORD);
|
|
mmio_write_32(CPG_CPGWPCR, CPGWPCR_PASSWORD);
|
|
|
|
reg = mmio_read_32(RCAR_PRR);
|
|
if ((reg & RCAR_CPU_MASK_CA57) == RCAR_CPU_HAVE_CA57)
|
|
mmio_write_32(CPG_CA57DBGRCR,
|
|
DBGCPUPREN | mmio_read_32(CPG_CA57DBGRCR));
|
|
|
|
if ((reg & RCAR_CPU_MASK_CA53) == RCAR_CPU_HAVE_CA53)
|
|
mmio_write_32(CPG_CA53DBGRCR,
|
|
DBGCPUPREN | mmio_read_32(CPG_CA53DBGRCR));
|
|
|
|
if (product_cut == RCAR_PRODUCT_H3_CUT10) {
|
|
reg = mmio_read_32(CPG_PLL2CR);
|
|
reg &= ~((uint32_t) 1 << 5);
|
|
mmio_write_32(CPG_PLL2CR, reg);
|
|
|
|
reg = mmio_read_32(CPG_PLL4CR);
|
|
reg &= ~((uint32_t) 1 << 5);
|
|
mmio_write_32(CPG_PLL4CR, reg);
|
|
|
|
reg = mmio_read_32(CPG_PLL0CR);
|
|
reg &= ~((uint32_t) 1 << 12);
|
|
mmio_write_32(CPG_PLL0CR, reg);
|
|
}
|
|
#if (RCAR_LOSSY_ENABLE == 1)
|
|
NOTICE("BL2: Lossy Decomp areas\n");
|
|
bl2_lossy_setting(0, LOSSY_ST_ADDR0, LOSSY_END_ADDR0,
|
|
LOSSY_FMT0, LOSSY_ENA_DIS0);
|
|
bl2_lossy_setting(1, LOSSY_ST_ADDR1, LOSSY_END_ADDR1,
|
|
LOSSY_FMT1, LOSSY_ENA_DIS1);
|
|
bl2_lossy_setting(2, LOSSY_ST_ADDR2, LOSSY_END_ADDR2,
|
|
LOSSY_FMT2, LOSSY_ENA_DIS2);
|
|
#endif
|
|
|
|
if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 ||
|
|
boot_dev == MODEMR_BOOT_DEV_EMMC_50X8)
|
|
rcar_io_emmc_setup();
|
|
else
|
|
rcar_io_setup();
|
|
}
|
|
|
|
void bl2_el3_plat_arch_setup(void)
|
|
{
|
|
#if RCAR_BL2_DCACHE == 1
|
|
NOTICE("BL2: D-Cache enable\n");
|
|
rcar_configure_mmu_el3(BL2_BASE,
|
|
RCAR_SYSRAM_LIMIT - BL2_BASE,
|
|
BL2_RO_BASE, BL2_RO_LIMIT
|
|
#if USE_COHERENT_MEM
|
|
, BL2_COHERENT_RAM_BASE, BL2_COHERENT_RAM_LIMIT
|
|
#endif
|
|
);
|
|
#endif
|
|
}
|
|
|
|
void bl2_platform_setup(void)
|
|
{
|
|
|
|
}
|