laurenw-arm 80942622fe Neoverse N1 Errata Workaround 1542419 ... Coherent I-cache is causing a prefetch violation where when the core executes an instruction that has recently been modified, the core might fetch a stale instruction which violates the ordering of instruction fetches. The workaround includes an instruction sequence to implementation defined registers to trap all EL0 IC IVAU instructions to EL3 and a trap handler to execute a TLB inner-shareable invalidation to an arbitrary address followed by a DSB. Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: Ic3b7cbb11cf2eaf9005523ef5578a372593ae4d6		2019-10-04 19:31:24 +03:00
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aarch32	Replace __ASSEMBLY__ with compiler-builtin __ASSEMBLER__	2019-08-01 13:14:12 -07:00
aarch64	Neoverse N1 Errata Workaround 1542419	2019-10-04 19:31:24 +03:00
errata_report.h	Replace __ASSEMBLY__ with compiler-builtin __ASSEMBLER__	2019-08-01 13:14:12 -07:00
wa_cve_2017_5715.h	Fix MISRA defects in workaround and errata framework	2018-10-29 14:41:48 +00:00
wa_cve_2018_3639.h	Fix MISRA defects in workaround and errata framework	2018-10-29 14:41:48 +00:00