Commit Graph

137 Commits

Author SHA1 Message Date
laurenw-arm 80942622fe Neoverse N1 Errata Workaround 1542419
Coherent I-cache is causing a prefetch violation where when the core
executes an instruction that has recently been modified, the core might
fetch a stale instruction which violates the ordering of instruction
fetches.

The workaround includes an instruction sequence to implementation
defined registers to trap all EL0 IC IVAU instructions to EL3 and a trap
handler to execute a TLB inner-shareable invalidation to an arbitrary
address followed by a DSB.

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: Ic3b7cbb11cf2eaf9005523ef5578a372593ae4d6
2019-10-04 19:31:24 +03:00
Artsem Artsemenka a4668c36f1 Cortex_hercules: Add support for Hercules-AE
Not tested on FVP Model.

Change-Id: Iedebc5c1fbc7ea577e94142b7feafa5546f1f4f9
Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.com>
2019-09-30 12:55:31 +01:00
kenny liang 7352f329e8 mediatek: mt8183: support CPU hotplug
- Add DCM driver
- Add SPMC driver
- Implement core and cluster power on/off handlers

Change-Id: I902002f8ea6f98fd73bf259188162b10d3939c72
Signed-off-by: kenny liang <kenny.liang@mediatek.com>
2019-09-10 11:25:08 +08:00
Julius Werner d5dfdeb65f Replace __ASSEMBLY__ with compiler-builtin __ASSEMBLER__
NOTE: __ASSEMBLY__ macro is now deprecated in favor of __ASSEMBLER__.

All common C compilers predefine a macro called __ASSEMBLER__ when
preprocessing a .S file. There is no reason for TF-A to define it's own
__ASSEMBLY__ macro for this purpose instead. To unify code with the
export headers (which use __ASSEMBLER__ to avoid one extra dependency),
let's deprecate __ASSEMBLY__ and switch the code base over to the
predefined standard.

Change-Id: Id7d0ec8cf330195da80499c68562b65cb5ab7417
Signed-off-by: Julius Werner <jwerner@chromium.org>
2019-08-01 13:14:12 -07:00
Balint Dobszay 3d08461a2d Enable AMU for Cortex-Hercules
Change-Id: Ie0a94783d0c8e111ae19fd592304e6485f04ca29
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>
2019-07-31 15:04:03 +00:00
Louis Mayencourt 294f9ef9f9 Cortex_hercules: Introduce preliminary cpu support
Change-Id: Iab767e9937f5c6c8150953fcdc3b37e8ee83fa63
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
2019-07-16 16:36:51 +01:00
Balint Dobszay f363deb6d4 Rename Cortex-Deimos to Cortex-A77
Change-Id: I755e4c42242d9a052570fd1132ca3d937acadb13
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>
2019-07-10 12:14:20 +02:00
lauwal01 11c48370bd Workaround for Neoverse N1 erratum 1262888
Neoverse N1 erratum 1262888 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set a bit in the implementation defined
CPUECTLR_EL1 system register, which disables the MMU hardware prefetcher.

[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html

Change-Id: Ib733d748e32a7ea6a2783f3d5a9c5e13eee01105
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-07-02 09:17:17 -05:00
lauwal01 411f4959b4 Workaround for Neoverse N1 erratum 1262606
Neoverse N1 erratum 1262606 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set a bit in the implementation defined
CPUACTLR_EL1 system register, which delays instruction fetch after
branch misprediction.

[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html

Change-Id: Idd980e9d5310232d38f0ce272862e1fb0f02ce9a
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-07-02 09:16:54 -05:00
lauwal01 335b3c79c7 Workaround for Neoverse N1 erratum 1257314
Neoverse N1 erratum 1257314 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set a bit in the implementation defined
CPUACTLR3_EL1 system register, which prevents parallel
execution of divide and square root instructions.

[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html

Change-Id: I54f0f40ff9043efee40d51e796b92ed85b394cbb
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-07-02 09:16:32 -05:00
lauwal01 9eceb020d7 Workaround for Neoverse N1 erratum 1220197
Neoverse N1 erratum 1220197 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set two bits in the implementation defined
CPUECTLR_EL1 system register, which disables write streaming to the L2.

[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html

Change-Id: I9c3373f1b6d67d21ee71b2b80aec5e96826818e8
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-07-02 09:16:10 -05:00
lauwal01 ef5fa7d477 Workaround for Neoverse N1 erratum 1207823
Neoverse N1 erratum 1207823 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set a bit in the implementation defined
CPUACTLR2_EL1 system register.

[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html

Change-Id: Ia932337821f1ef0d644db3612480462a8d924d21
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-07-02 09:15:48 -05:00
lauwal01 2017ab241c Workaround for Neoverse N1 erratum 1165347
Neoverse N1 erratum 1165347 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set two bits in the implementation defined
CPUACTLR2_EL1 system register.

[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html

Change-Id: I163d0ea00578245c1323d2340314cdc3088c450d
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-07-02 09:15:15 -05:00
lauwal01 e34606f2e4 Workaround for Neoverse N1 erratum 1130799
Neoverse N1 erratum 1130799 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set a bit in the implementation defined
CPUACTLR2_EL1 system register.

[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html

Change-Id: I252bc45f9733443ba0503fefe62f50fdea61da6d
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-07-02 09:14:54 -05:00
lauwal01 a601afe158 Workaround for Neoverse N1 erratum 1073348
Neoverse N1 erratum 1073348 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set a bit in the implementation defined
CPUACTLR_EL1 system register, which disables static prediction.

[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html

Change-Id: I674126c0af6e068eecb379a190bcf7c75dcbca8e
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-07-02 09:13:31 -05:00
Andre Przywara 5f5d076387 Neoverse N1: Introduce workaround for Neoverse N1 erratum 1315703
Neoverse N1 erratum 1315703 is a Cat A (rare) erratum [1], present in
older revisions of the Neoverse N1 processor core.
The workaround is to set a bit in the implementation defined CPUACTLR2_EL1
system register, which will disable the load-bypass-store feature.

[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdocpjdoc-466751330-1032/index.html

Change-Id: I5c708dbe0efa4daa0bcb6bd9622c5efe19c03af9
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2019-06-06 14:27:37 +01:00
Ambroise Vincent 9af07df050 Cortex-A55: workarounds for errata 1221012
The workaround is added to the Cortex-A55 cpu specific file. The
workaround is disabled by default and have to be explicitly enabled by
the platform integrator.

Change-Id: I3e6fd10df6444122a8ee7d08058946ff1cc912f8
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-05-28 14:19:04 +01:00
Soby Mathew e6e1d0ac16 Cortex-A76: workarounds for errata 1257314, 1262606, 1262888, 1275112
The workarounds for errata 1257314, 1262606, 1262888 and 1275112 are
added to the Cortex-A76 cpu specific file. The workarounds are disabled
by default and have to be explicitly enabled by the platform integrator.

Change-Id: I70474927374cb67725f829d159ddde9ac4edc343
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2019-05-07 13:46:47 +01:00
Louis Mayencourt 632ab3eb26 Neoverse N1: Forces cacheable atomic to near
This patch forces all cacheable atomic instructions to be near, which
improves performance in highly contended parallelized use-cases.

Change-Id: I93fac62847f4af8d5eaaf3b52318c30893e947d3
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
2019-04-18 14:55:46 +01:00
Louis Mayencourt 0e985d708e DSU: Implement workaround for errata 798953
Under certain near idle conditions, DSU may miss response transfers on
the ACE master or Peripheral port, leading to deadlock. This workaround
disables high-level clock gating of the DSU to prevent this.

Change-Id: I820911d61570bacb38dd325b3519bc8d12caa14b
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
2019-04-17 13:46:43 +01:00
Louis Mayencourt 2c3b76ce7b DSU: Small fix and reformat on errata framework
Change-Id: I50708f6ccc33059fbfe6d36fd66351f0b894311f
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
2019-04-17 13:46:43 +01:00
Louis Mayencourt cba71b70ef Cortex-A35: Implement workaround for errata 855472
Under specific conditions, the processor might issue an eviction and an
L2 cache clean operation to the interconnect in the wrong order. Set
the CPUACTLR.ENDCCASCI bit to 1 to avoid this.

Change-Id: Ide7393adeae04581fa70eb9173b742049fc3e050
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
2019-04-17 13:46:43 +01:00
Antonio Niño Díaz 72562aab00 Merge "cpus: Fix Cortex-A12 MIDR mask" into integration 2019-04-09 10:50:52 +00:00
Alexei Fedorov 9ccc5a5733 Add support for Cortex-A76AE CPU
Change-Id: I0a81f4ea94d41245cd5150de341b51fc70babffe
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
2019-04-08 14:48:55 +01:00
Heiko Stuebner 8785a7cf72 cpus: Fix Cortex-A12 MIDR mask
The Cortex-A12's primary part number is 0xC0D not 0xC0C, so
fix that to make the A12's cpu operations findable.

Change-Id: I4440a039cd57a2fe425fd8a8ec5499ca8e895e31
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-04-08 12:47:48 +02:00
Soby Mathew 75044d8b87
Merge pull request #1894 from jts-arm/e1_midr
Fix MIDR_EL1 value for Neoverse E1
2019-03-18 16:15:12 +00:00
John Tsichritzis c4187c9c4b Fix wrong MIDR_EL1 value for Neoverse E1
Change-Id: I75ee39d78c81ecb528a671c0cfadfc2fe7b5d818
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-03-15 15:40:27 +00:00
John Tsichritzis a4546e80f5 Introduce preliminary support for Neoverse Zeus
Change-Id: If56d1e200a31bd716726d7fdc1cc0ae8a63ba3ee
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-03-14 11:39:40 +00:00
Ambroise Vincent 0b64c19485 Cortex-A17: Implement workaround for errata 852421
Change-Id: Ic3004fc43229d63c5a59ca74c1837fb0604e1f33
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-03-13 15:40:45 +00:00
Ambroise Vincent 5f2c690d0e Cortex-A15: Implement workaround for errata 827671
This erratum can only be worked around on revisions >= r3p0 because the
register that needs to be accessed only exists in those revisions[1].

[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0438g/CIHEAAAD.html

Change-Id: I5d773547d7a09b5bd01dabcd19ceeaf53c186faa
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-03-13 14:05:47 +00:00
Antonio Niño Díaz 37118a1b5f
Merge pull request #1849 from loumay-arm/lm/a73_errata
Cortex-A73: Implement workaround for errata 852427
2019-03-01 11:23:48 +00:00
Antonio Niño Díaz 4476838ae8
Merge pull request #1845 from ambroise-arm/av/errata
Apply workarounds for errata of Cortex-A53, A55 and A57
2019-03-01 09:17:27 +00:00
Louis Mayencourt 25278eaba7 Cortex-A73: Implement workaround for errata 852427
In AArch32, execution of 2 instructions with opposite condition code
might lead to either a data corruption or a CPU deadlock. Set the bit
12 of the Diagnostic Register to prevent this.

Change-Id: I22b4f25fe933e2942fd785e411e7c0aa39d5c1f4
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
2019-02-28 12:01:13 +00:00
Ambroise Vincent 0f6fbbd2e5 Cortex-A57: Implement workaround for erratum 814670
Change-Id: Ice3dcba8c46cea070fd4ca3ffb32aedc840589ad
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-02-28 09:56:58 +00:00
Ambroise Vincent 6ab87d2981 Cortex-A55: Implement workaround for erratum 798797
Change-Id: Ic42b37b8500d5e592af2b9fe130f35a0e2db4d14
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-02-28 09:56:58 +00:00
Ambroise Vincent a6cc661016 Cortex-A55: Implement workaround for erratum 778703
Change-Id: I094e5cb2c44618e7a4116af5fbb6b18078a79951
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-02-28 09:56:58 +00:00
Ambroise Vincent 1afeee9275 Cortex-A55: Implement workaround for erratum 768277
Change-Id: Iebd45ef5e39ee7080235fb85414ce5b2e776f90c
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-02-28 09:56:58 +00:00
Louis Mayencourt 5c6aa01aff Add workaround for errata 1073348 for Cortex-A76
Concurrent instruction TLB miss and mispredicted return instruction
might fetch wrong instruction stream. Set bit 6 of CPUACTLR_EL1 to
prevent this.

Change-Id: I2da4f30cd2df3f5e885dd3c4825c557492d1ac58
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
2019-02-26 16:21:06 +00:00
Louis Mayencourt 5cc8c7ba1b Add workaround for errata 1220197 for Cortex-A76
Streaming store under specific conditions might cause deadlock or data
corruption. Set bit 25:24 of CPUECTLR_EL1, which disables write
streaming to the L2 to prevent this.

Change-Id: Ib5cabb997b35ada78b27e75787afd610ea606dcf
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
2019-02-26 16:21:06 +00:00
Louis Mayencourt e6cab15dc7 Add workaround for errata 855423 of Cortex-A73
Broadcast maintainance operations might not be correctly synchronized
between cores. Set bit 7 of S3_0_C15_C0_2 to prevent this.

Change-Id: I67fb62c0b458d44320ebaedafcb8495ff26c814b
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
2019-02-26 13:22:56 +00:00
Antonio Niño Díaz 3f995f3078
Merge pull request #1835 from jts-arm/rename
Apply official names to new Arm Neoverse cores
2019-02-22 13:05:37 +00:00
John Tsichritzis 11088e3924 Rename Cortex-Helios to Neoverse E1
Change-Id: I1adcf195c0ba739002f3a59e805c782dd292ccba
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-02-19 14:02:34 +00:00
John Tsichritzis fd4bb0ad4b Rename Cortex-Helios filenames to Neoverse E1
Change-Id: I33bdb9df0462b056adbd00922b2e73eb720560b3
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-02-19 14:02:29 +00:00
John Tsichritzis da6d75a0e7 Rename Cortex-Ares to Neoverse N1
Change-Id: Ideb49011da35f39ff1959be6f5015fa212ca2b6b
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-02-19 13:50:07 +00:00
John Tsichritzis b04ea14b79 Rename Cortex-Ares filenames to Neoverse N1
Change-Id: I0bb5aca9bb272332340b5baefc473a01f8a27896
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-02-19 13:49:59 +00:00
Antonio Nino Diaz ff6f62e105 Update macro to check need for CVE-2017-5715 mitigation
Armv8.5 introduces the field CSV2 to register ID_AA64PFR0_EL1. It can
have the following 3 values:

- 0: Branch targets trained in one hardware described context may affect
     speculative execution in a different hardware described context. In
     some CPUs it may be needed to apply mitigations.

- 1: Branch targets trained in one hardware described context can only
     affect speculative execution in a different hardware described
     context in a hard-to-determine way. No mitigation required.

- 2: Same as 1, but the device is also aware of SCXTNUM_ELx register
     contexts. The TF doesn't use the registers, so there is no
     difference with 1.

The field CSV2 was originally introduced in the TRM of the Cortex-A76
before the release of the Armv8.5 architecture. That TRM only mentions
the meaning of values 0 and 1. Because of this, the code only checks if
the field has value 1 to know whether to enable or disable the
mitigations.

This patch makes it aware of value 2 as well. Both values 1 and 2
disable the mitigation, and 0 enables it.

Change-Id: I5af33de25a0197c98173f52c6c8c77b51a51429f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2019-02-14 14:43:43 +00:00
Antonio Nino Diaz 1a74e4a895 cpus: Add casts to all definitions in CPU headers
There are some incorrect casts and some missing casts in the headers.
This patch fixes the ones that were 64-bit or 32-bit wide wrongly and
adds casts where they were missing.

Note that none of the changes of the patch actually changes the values
of the definitions. This patch is just for correctness.

Change-Id: Iad6458021bad521922ce4f91bafff38b116b49eb
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2019-02-11 13:34:57 +00:00
Antonio Nino Diaz a69817eda2 cpus: Fix some incorrect definitions in CPU headers
There are some values that should be 64-bit immediates but that resolve
to 0 because the type of the value is 32-bit wide. This patch casts the
expressions to 64-bit before the shift so that the definition has the
correct value.

The definitions are only used in assembly so far, so the code is not
actually affected by this bug. The assembler treats all values as 64-bit
values, so there are no overflows.

Change-Id: I965e4be631c1d28787c0913661d224c82a6b9155
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2019-02-11 13:34:54 +00:00
Antonio Nino Diaz 09d40e0e08 Sanitise includes across codebase
Enforce full include path for includes. Deprecate old paths.

The following folders inside include/lib have been left unchanged:

- include/lib/cpus/${ARCH}
- include/lib/el3_runtime/${ARCH}

The reason for this change is that having a global namespace for
includes isn't a good idea. It defeats one of the advantages of having
folders and it introduces problems that are sometimes subtle (because
you may not know the header you are actually including if there are two
of them).

For example, this patch had to be created because two headers were
called the same way: e0ea0928d5 ("Fix gpio includes of mt8173 platform
to avoid collision."). More recently, this patch has had similar
problems: 46f9b2c3a2 ("drivers: add tzc380 support").

This problem was introduced in commit 4ecca33988 ("Move include and
source files to logical locations"). At that time, there weren't too
many headers so it wasn't a real issue. However, time has shown that
this creates problems.

Platforms that want to preserve the way they include headers may add the
removed paths to PLAT_INCLUDES, but this is discouraged.

Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2019-01-04 10:43:17 +00:00
Antonio Nino Diaz c3cf06f1a3 Standardise header guards across codebase
All identifiers, regardless of use, that start with two underscores are
reserved. This means they can't be used in header guards.

The style that this project is now to use the full name of the file in
capital letters followed by 'H'. For example, for a file called
"uart_example.h", the header guard is UART_EXAMPLE_H.

The exceptions are files that are imported from other projects:

- CryptoCell driver
- dt-bindings folders
- zlib headers

Change-Id: I50561bf6c88b491ec440d0c8385c74650f3c106e
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-11-08 10:20:19 +00:00