MMC sample select needs to be set properly so that DWMMC clock can be driven to 50Mhz Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com> Change-Id: I4a1dde4f6a1e78a36940c57a7a5b162be0bd443a |
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s10_clock_manager.c | ||
s10_handoff.c | ||
s10_mailbox.c | ||
s10_memory_controller.c | ||
s10_pinmux.c | ||
s10_reset_manager.c | ||
s10_system_manager.c |