arm-trusted-firmware/bl1
Soby Mathew 8cd16e6b5b Build option to include AArch32 registers in cpu context
The system registers that are saved and restored in CPU context include
AArch32 systems registers like SPSR_ABT, SPSR_UND, SPSR_IRQ, SPSR_FIQ,
DACR32_EL2, IFSR32_EL2 and FPEXC32_EL2. Accessing these registers on an
AArch64-only (i.e. on hardware that does not implement AArch32, or at
least not at EL1 and higher ELs) platform leads to an exception. This patch
introduces the build option `CTX_INCLUDE_AARCH32_REGS` to specify whether to
include these AArch32 systems registers in the cpu context or not. By default
this build option is set to 1 to ensure compatibility. AArch64-only platforms
must set it to 0. A runtime check is added in BL1 and BL31 cold boot path to
verify this.

Fixes ARM-software/tf-issues#386

Change-Id: I720cdbd7ed7f7d8516635a2ec80d025f478b95ee
2016-06-03 10:50:52 +01:00
..
aarch64 Enable asynchronous abort exceptions during boot 2016-03-30 17:26:23 +02:00
tbbr Fix the inconsistencies in bl1_tbbr_image_descs[] 2016-02-22 18:17:34 +00:00
bl1.ld.S TBB: add authentication framework 2015-06-25 08:53:26 +01:00
bl1.mk FWU: Add Generic Firmware Update framework support in BL1 2015-12-09 17:41:18 +00:00
bl1_context_mgmt.c Build option to include AArch32 registers in cpu context 2016-06-03 10:50:52 +01:00
bl1_fwu.c Fix the inconsistencies in bl1_tbbr_image_descs[] 2016-02-22 18:17:34 +00:00
bl1_main.c Remove dashes from image names: 'BL3-x' --> 'BL3x' 2015-12-14 12:31:37 +00:00
bl1_private.h FWU: Add Generic Firmware Update framework support in BL1 2015-12-09 17:41:18 +00:00