Louis Mayencourt 98551591f5 Add workaround for errata 790748 for Cortex-A75 ... Internal timing conditions might cause the CPU to stop processing interrupts. Set bit 13 of CPUACTLR_EL1 to prevent this. Change-Id: Ifdd19dbcdb71bb0d9609cab1315c478aaedb03ba Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>		2019-02-26 16:20:59 +00:00
..
aarch32	Sanitise includes across codebase	2019-01-04 10:43:17 +00:00
aarch64	Add workaround for errata 790748 for Cortex-A75	2019-02-26 16:20:59 +00:00
cpu-ops.mk	Add workaround for errata 790748 for Cortex-A75	2019-02-26 16:20:59 +00:00
errata_report.c	Sanitise includes across codebase	2019-01-04 10:43:17 +00:00