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Upstream fork of ATF with a couple of rk3399 patches to remove HDCP blob and increase BAUD_RATE.
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Dimitris Papastamos a1781a211a Workaround for CVE-2017-5715 on Cortex A73 and A75 
Invalidate the Branch Target Buffer (BTB) on entry to EL3 by
temporarily dropping into AArch32 Secure-EL1 and executing the
`BPIALL` instruction.

This is achieved by using 3 vector tables.  There is the runtime
vector table which is used to handle exceptions and 2 additional
tables which are required to implement this workaround.  The
additional tables are `vbar0` and `vbar1`.

The sequence of events for handling a single exception is
as follows:

1) Install vector table `vbar0` which saves the CPU context on entry
   to EL3 and sets up the Secure-EL1 context to execute in AArch32 mode
   with the MMU disabled and I$ enabled.  This is the default vector table.

2) Before doing an ERET into Secure-EL1, switch vbar to point to
   another vector table `vbar1`.  This is required to restore EL3 state
   when returning from the workaround, before proceeding with normal EL3
   exception handling.

3) While in Secure-EL1, the `BPIALL` instruction is executed and an
   SMC call back to EL3 is performed.

4) On entry to EL3 from Secure-EL1, the saved context from step 1) is
   restored.  The vbar is switched to point to `vbar0` in preparation to
   handle further exceptions.  Finally a branch to the runtime vector
   table entry is taken to complete the handling of the original
   exception.

This workaround is enabled by default on the affected CPUs.

NOTE
====

There are 4 different stubs in Secure-EL1.  Each stub corresponds to
an exception type such as Sync/IRQ/FIQ/SError.  Each stub will move a
different value in `R0` before doing an SMC call back into EL3.
Without this piece of information it would not be possible to know
what the original exception type was as we cannot use `ESR_EL3` to
distinguish between IRQs and FIQs.

Change-Id: I90b32d14a3735290b48685d43c70c99daaa4b434
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
 		2018-01-11 10:26:15 +00:00
bl1 Replace magic numbers in linkerscripts by PAGE_SIZE 2017-11-29 12:09:52 +00:00
bl2 Replace magic numbers in linkerscripts by PAGE_SIZE 2017-11-29 12:09:52 +00:00
bl2u Replace magic numbers in linkerscripts by PAGE_SIZE 2017-11-29 12:09:52 +00:00
bl31 Workaround for CVE-2017-5715 on Cortex A73 and A75 2018-01-11 10:26:15 +00:00
bl32 Merge pull request #1174 from antonio-nino-diaz-arm/an/page-size 2017-12-08 16:29:19 +00:00
common Add support to left-pad with zeroes in tf_printf 2017-12-15 15:03:48 +00:00
docs Workaround for CVE-2017-5715 on Cortex A57 and A72 2018-01-11 10:26:15 +00:00
drivers Merge pull request #1194 from robertovargas-arm/io-fix 2017-12-19 17:39:20 +00:00
fdts Add Linux DTS for FVP with threaded CPUs 2017-08-01 14:33:47 +01:00
include Workaround for CVE-2017-5715 on Cortex A73 and A75 2018-01-11 10:26:15 +00:00
lib Workaround for CVE-2017-5715 on Cortex A73 and A75 2018-01-11 10:26:15 +00:00
make_helpers Build: specify check_* targets as .PHONY 2017-12-24 22:45:53 +09:00
plat Merge pull request #1176 from wjliang/zynqmp-ipi-mb-svc 2018-01-10 14:57:22 +00:00
services SPM: Allow secondary CPUs to use the Secure Partition 2018-01-08 09:59:33 +00:00
tools Add padding at the end of the last entry 2018-01-03 20:51:43 +00:00
.checkpatch.conf Mandate 'Signed-off-by' line in commit messages 2016-10-24 13:44:59 +01:00
.gitignore fip: move headers shared between TF and fiptool to include/tools_share 2017-05-23 23:58:47 +09:00
Makefile Disable PIE compilation option 2017-12-14 23:36:15 +00:00
acknowledgements.rst Convert documentation to reStructuredText 2017-06-29 11:47:09 +01:00
contributing.rst Convert documentation to reStructuredText 2017-06-29 11:47:09 +01:00
dco.txt Drop requirement for CLA in contribution.md 2016-09-27 21:52:03 +01:00
license.rst Convert documentation to reStructuredText 2017-06-29 11:47:09 +01:00
maintainers.rst Miscellaneous fixes to maintainers.rst 2017-12-06 16:36:43 +00:00
readme.rst Clarify third party license info in readme 2017-07-17 15:19:37 +01:00

readme.rst

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ARM Trusted Firmware - version 1.4

ARM Trusted Firmware provides a reference implementation of secure world software for ARMv8-A, including a Secure Monitor executing at Exception Level 3 (EL3). It implements various ARM interface standards, such as:

As far as possible the code is designed for reuse or porting to other ARMv8-A model and hardware platforms.

ARM will continue development in collaboration with interested parties to provide a full reference implementation of Secure Monitor code and ARM standards to the benefit of all developers working with ARMv8-A TrustZone technology.

License

The software is provided under a BSD-3-Clause license. Contributions to this project are accepted under the same license with developer sign-off as described in the Contributing Guidelines.

This project contains code from other projects as listed below. The original license text is included in those source files.

  • The stdlib source code is derived from FreeBSD code, which uses various BSD licenses, including BSD-3-Clause and BSD-2-Clause.
  • The libfdt source code is dual licensed. It is used by this project under the terms of the BSD-2-Clause license.
  • The LLVM compiler-rt source code is dual licensed. It is used by this project under the terms of the NCSA license (also known as the University of Illinois/NCSA Open Source License).

This Release

This release provides a suitable starting point for productization of secure world boot and runtime firmware, in either the AArch32 or AArch64 execution state.

Users are encouraged to do their own security validation, including penetration testing, on any secure world code derived from ARM Trusted Firmware.

Functionality

  • Initialization of the secure world, for example exception vectors, control registers and interrupts for the platform.
  • Library support for CPU specific reset and power down sequences. This includes support for errata workarounds and the latest ARM DynamIQ CPUs.
  • Drivers to enable standard initialization of ARM System IP, for example Generic Interrupt Controller (GIC), Cache Coherent Interconnect (CCI), Cache Coherent Network (CCN), Network Interconnect (NIC) and TrustZone Controller (TZC).
  • A generic SCMI driver to interface with conforming power controllers, for example the ARM System Control Processor (SCP).
  • SMC (Secure Monitor Call) handling, conforming to the SMC Calling Convention using an EL3 runtime services framework.
  • PSCI library support for CPU, cluster and system power management use-cases. This library is pre-integrated with the AArch64 EL3 Runtime Software, and is also suitable for integration with other AArch32 EL3 Runtime Software, for example an AArch32 Secure OS.
  • A minimal AArch32 Secure Payload (SP_MIN) to demonstrate PSCI library integration with AArch32 EL3 Runtime Software.
  • Secure Monitor library code such as world switching, EL1 context management and interrupt routing. When a Secure-EL1 Payload (SP) is present, for example a Secure OS, the AArch64 EL3 Runtime Software must be integrated with a dispatcher component (SPD) to customize the interaction with the SP.
  • A Test SP/SPD to demonstrate AArch64 Secure Monitor functionality and SP interaction with PSCI.
  • SPDs for the OP-TEE Secure OS, NVidia Trusted Little Kernel and Trusty Secure OS.
  • A Trusted Board Boot implementation, conforming to all mandatory TBBR requirements. This includes image authentication, Firmware Update (or recovery mode), and packaging of the various firmware images into a Firmware Image Package (FIP).
  • Pre-integration of TBB with the ARM TrustZone CryptoCell product, to take advantage of its hardware Root of Trust and crypto acceleration services.
  • Support for alternative boot flows, for example to support platforms where the EL3 Runtime Software is loaded using other firmware or a separate secure system processor.
  • Support for the GCC, LLVM and ARM Compiler 6 toolchains.

For a full description of functionality and implementation details, please see the Firmware Design and supporting documentation. The Change Log provides details of changes made since the last release.

Platforms

Various AArch32 and AArch64 builds of this release has been tested on variants r0, r1 and r2 of the Juno ARM Development Platform.

Various AArch64 builds of this release have been tested on the following ARM FVPs (64-bit host machine only):

NOTE: Unless otherwise stated, the FVP Version is 11.0, Build 11.0.34.

  • Foundation_Platform
  • FVP_Base_AEMv8A-AEMv8A (Version 8.5, Build 0.8.8502)
  • FVP_Base_Cortex-A35x4
  • FVP_Base_Cortex-A53x4
  • FVP_Base_Cortex-A57x4-A53x4
  • FVP_Base_Cortex-A57x4
  • FVP_Base_Cortex-A72x4-A53x4
  • FVP_Base_Cortex-A72x4
  • FVP_Base_Cortex-A73x4-A53x4
  • FVP_Base_Cortex-A73x4
  • FVP_CSS_SGM-775 (Version 11.0, Build 11.0.36)

Various AArch32 builds of this release has been tested on the following ARM FVPs (64-bit host machine only):

  • FVP_Base_AEMv8A-AEMv8A (Version 8.5, Build 0.8.8502)
  • FVP_Base_Cortex-A32x4

The Foundation FVP can be downloaded free of charge. The Base FVPs can be licensed from ARM. See the ARM FVP website.

All the above platforms have been tested with Linaro Release 17.04.

This release also contains the following platform support:

  • HiKey and HiKey960 boards
  • MediaTek MT6795 and MT8173 SoCs
  • NVidia T132, T186 and T210 SoCs
  • QEMU emulator
  • RockChip RK3328, RK3368 and RK3399 SoCs
  • Socionext UniPhier SoC family
  • Xilinx Zynq UltraScale + MPSoC

Still to Come

  • More platform support.
  • Ongoing support for new architectural features, CPUs and System IP.
  • Ongoing support for new PSCI, SCMI and TBBR features.
  • Ongoing security hardening, optimization and quality improvements.

For a full list of detailed issues in the current code, please see the Change Log and the GitHub issue tracker.

Getting Started

Get the Trusted Firmware source code from GitHub.

See the User Guide for instructions on how to install, build and use the Trusted Firmware with the ARM FVPs.

See the Firmware Design for information on how the Trusted Firmware works.

See the Porting Guide as well for information about how to use this software on another ARMv8-A platform.

See the Contributing Guidelines for information on how to contribute to this project and the Acknowledgments file for a list of contributors to the project.

Feedback and support

ARM welcomes any feedback on Trusted Firmware. If you think you have found a security vulnerability, please report this using the process defined in the Trusted Firmware Security Centre. For all other feedback, please use the GitHub issue tracker.

ARM licensees may contact ARM directly via their partner managers.

Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.

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