373 lines
13 KiB
ArmAsm
373 lines
13 KiB
ArmAsm
/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <context.h>
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.globl workaround_bpiall_vbar0_runtime_exceptions
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#define EMIT_BPIALL 0xee070fd5
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#define EMIT_MOV_R0_IMM(v) 0xe3a0000##v
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#define EMIT_SMC 0xe1600070
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.macro enter_workaround _stub_name
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/* Save GP regs */
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stp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
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stp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
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stp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
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stp x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6]
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stp x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8]
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stp x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10]
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stp x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12]
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stp x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14]
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stp x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16]
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stp x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18]
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stp x20, x21, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X20]
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stp x22, x23, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X22]
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stp x24, x25, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X24]
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stp x26, x27, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X26]
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stp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28]
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adr x4, \_stub_name
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/*
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* Load SPSR_EL3 and VBAR_EL3. SPSR_EL3 is set up to have
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* all interrupts masked in preparation to running the workaround
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* stub in S-EL1. VBAR_EL3 points to the vector table that
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* will handle the SMC back from the workaround stub.
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*/
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ldp x0, x1, [x4, #0]
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/*
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* Load SCTLR_EL1 and ELR_EL3. SCTLR_EL1 is configured to disable
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* the MMU in S-EL1. ELR_EL3 points to the appropriate stub in S-EL1.
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*/
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ldp x2, x3, [x4, #16]
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mrs x4, scr_el3
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mrs x5, spsr_el3
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mrs x6, elr_el3
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mrs x7, sctlr_el1
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mrs x8, esr_el3
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/* Preserve system registers in the workaround context */
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stp x4, x5, [sp, #CTX_CVE_2017_5715_OFFSET + CTX_CVE_2017_5715_QUAD0]
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stp x6, x7, [sp, #CTX_CVE_2017_5715_OFFSET + CTX_CVE_2017_5715_QUAD2]
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stp x8, x30, [sp, #CTX_CVE_2017_5715_OFFSET + CTX_CVE_2017_5715_QUAD4]
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/*
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* Setting SCR_EL3 to all zeroes means that the NS, RW
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* and SMD bits are configured as expected.
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*/
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msr scr_el3, xzr
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/*
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* Reload system registers with the crafted values
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* in preparation for entry in S-EL1.
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*/
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msr spsr_el3, x0
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msr vbar_el3, x1
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msr sctlr_el1, x2
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msr elr_el3, x3
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eret
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.endm
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/* ---------------------------------------------------------------------
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* This vector table is used at runtime to enter the workaround at
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* AArch32 S-EL1 for Sync/IRQ/FIQ/SError exceptions. If the workaround
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* is not enabled, the existing runtime exception vector table is used.
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* ---------------------------------------------------------------------
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*/
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vector_base workaround_bpiall_vbar0_runtime_exceptions
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/* ---------------------------------------------------------------------
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* Current EL with SP_EL0 : 0x0 - 0x200
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* ---------------------------------------------------------------------
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*/
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vector_entry workaround_bpiall_vbar0_sync_exception_sp_el0
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b sync_exception_sp_el0
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/*
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* Since each vector table entry is 128 bytes, we can store the
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* stub context in the unused space to minimize memory footprint.
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*/
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aarch32_stub_smc:
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.word EMIT_BPIALL
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.word EMIT_MOV_R0_IMM(1)
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.word EMIT_SMC
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aarch32_stub_ctx_smc:
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/* Mask all interrupts and set AArch32 Supervisor mode */
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.quad (SPSR_AIF_MASK << SPSR_AIF_SHIFT | \
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SPSR_M_AARCH32 << SPSR_M_SHIFT | \
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MODE32_svc << MODE32_SHIFT)
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/*
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* VBAR_EL3 points to vbar1 which is the vector table
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* used while the workaround is executing.
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*/
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.quad workaround_bpiall_vbar1_runtime_exceptions
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/* Setup SCTLR_EL1 with MMU off and I$ on */
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.quad SCTLR_AARCH32_EL1_RES1 | SCTLR_I_BIT
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/* ELR_EL3 is setup to point to the sync exception stub in AArch32 */
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.quad aarch32_stub_smc
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check_vector_size workaround_bpiall_vbar0_sync_exception_sp_el0
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vector_entry workaround_bpiall_vbar0_irq_sp_el0
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b irq_sp_el0
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aarch32_stub_irq:
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.word EMIT_BPIALL
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.word EMIT_MOV_R0_IMM(2)
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.word EMIT_SMC
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aarch32_stub_ctx_irq:
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.quad (SPSR_AIF_MASK << SPSR_AIF_SHIFT | \
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SPSR_M_AARCH32 << SPSR_M_SHIFT | \
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MODE32_svc << MODE32_SHIFT)
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.quad workaround_bpiall_vbar1_runtime_exceptions
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.quad SCTLR_AARCH32_EL1_RES1 | SCTLR_I_BIT
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.quad aarch32_stub_irq
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check_vector_size workaround_bpiall_vbar0_irq_sp_el0
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vector_entry workaround_bpiall_vbar0_fiq_sp_el0
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b fiq_sp_el0
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aarch32_stub_fiq:
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.word EMIT_BPIALL
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.word EMIT_MOV_R0_IMM(4)
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.word EMIT_SMC
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aarch32_stub_ctx_fiq:
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.quad (SPSR_AIF_MASK << SPSR_AIF_SHIFT | \
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SPSR_M_AARCH32 << SPSR_M_SHIFT | \
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MODE32_svc << MODE32_SHIFT)
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.quad workaround_bpiall_vbar1_runtime_exceptions
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.quad SCTLR_AARCH32_EL1_RES1 | SCTLR_I_BIT
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.quad aarch32_stub_fiq
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check_vector_size workaround_bpiall_vbar0_fiq_sp_el0
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vector_entry workaround_bpiall_vbar0_serror_sp_el0
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b serror_sp_el0
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aarch32_stub_serror:
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.word EMIT_BPIALL
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.word EMIT_MOV_R0_IMM(8)
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.word EMIT_SMC
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aarch32_stub_ctx_serror:
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.quad (SPSR_AIF_MASK << SPSR_AIF_SHIFT | \
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SPSR_M_AARCH32 << SPSR_M_SHIFT | \
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MODE32_svc << MODE32_SHIFT)
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.quad workaround_bpiall_vbar1_runtime_exceptions
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.quad SCTLR_AARCH32_EL1_RES1 | SCTLR_I_BIT
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.quad aarch32_stub_serror
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check_vector_size workaround_bpiall_vbar0_serror_sp_el0
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/* ---------------------------------------------------------------------
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* Current EL with SP_ELx: 0x200 - 0x400
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* ---------------------------------------------------------------------
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*/
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vector_entry workaround_bpiall_vbar0_sync_exception_sp_elx
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b sync_exception_sp_elx
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check_vector_size workaround_bpiall_vbar0_sync_exception_sp_elx
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vector_entry workaround_bpiall_vbar0_irq_sp_elx
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b irq_sp_elx
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check_vector_size workaround_bpiall_vbar0_irq_sp_elx
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vector_entry workaround_bpiall_vbar0_fiq_sp_elx
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b fiq_sp_elx
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check_vector_size workaround_bpiall_vbar0_fiq_sp_elx
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vector_entry workaround_bpiall_vbar0_serror_sp_elx
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b serror_sp_elx
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check_vector_size workaround_bpiall_vbar0_serror_sp_elx
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/* ---------------------------------------------------------------------
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* Lower EL using AArch64 : 0x400 - 0x600
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* ---------------------------------------------------------------------
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*/
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vector_entry workaround_bpiall_vbar0_sync_exception_aarch64
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enter_workaround aarch32_stub_ctx_smc
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check_vector_size workaround_bpiall_vbar0_sync_exception_aarch64
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vector_entry workaround_bpiall_vbar0_irq_aarch64
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enter_workaround aarch32_stub_ctx_irq
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check_vector_size workaround_bpiall_vbar0_irq_aarch64
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vector_entry workaround_bpiall_vbar0_fiq_aarch64
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enter_workaround aarch32_stub_ctx_fiq
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check_vector_size workaround_bpiall_vbar0_fiq_aarch64
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vector_entry workaround_bpiall_vbar0_serror_aarch64
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enter_workaround aarch32_stub_ctx_serror
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check_vector_size workaround_bpiall_vbar0_serror_aarch64
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/* ---------------------------------------------------------------------
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* Lower EL using AArch32 : 0x600 - 0x800
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* ---------------------------------------------------------------------
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*/
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vector_entry workaround_bpiall_vbar0_sync_exception_aarch32
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enter_workaround aarch32_stub_ctx_smc
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check_vector_size workaround_bpiall_vbar0_sync_exception_aarch32
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vector_entry workaround_bpiall_vbar0_irq_aarch32
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enter_workaround aarch32_stub_ctx_irq
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check_vector_size workaround_bpiall_vbar0_irq_aarch32
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vector_entry workaround_bpiall_vbar0_fiq_aarch32
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enter_workaround aarch32_stub_ctx_fiq
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check_vector_size workaround_bpiall_vbar0_fiq_aarch32
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vector_entry workaround_bpiall_vbar0_serror_aarch32
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enter_workaround aarch32_stub_ctx_serror
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check_vector_size workaround_bpiall_vbar0_serror_aarch32
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/* ---------------------------------------------------------------------
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* This vector table is used while the workaround is executing. It
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* installs a simple SMC handler to allow the Sync/IRQ/FIQ/SError
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* workaround stubs to enter EL3 from S-EL1. It restores the previous
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* EL3 state before proceeding with the normal runtime exception vector.
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* ---------------------------------------------------------------------
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*/
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vector_base workaround_bpiall_vbar1_runtime_exceptions
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/* ---------------------------------------------------------------------
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* Current EL with SP_EL0 : 0x0 - 0x200 (UNUSED)
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* ---------------------------------------------------------------------
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*/
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vector_entry workaround_bpiall_vbar1_sync_exception_sp_el0
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b report_unhandled_exception
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check_vector_size workaround_bpiall_vbar1_sync_exception_sp_el0
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vector_entry workaround_bpiall_vbar1_irq_sp_el0
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b report_unhandled_interrupt
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check_vector_size workaround_bpiall_vbar1_irq_sp_el0
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vector_entry workaround_bpiall_vbar1_fiq_sp_el0
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b report_unhandled_interrupt
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check_vector_size workaround_bpiall_vbar1_fiq_sp_el0
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vector_entry workaround_bpiall_vbar1_serror_sp_el0
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b report_unhandled_exception
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check_vector_size workaround_bpiall_vbar1_serror_sp_el0
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/* ---------------------------------------------------------------------
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* Current EL with SP_ELx: 0x200 - 0x400 (UNUSED)
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* ---------------------------------------------------------------------
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*/
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vector_entry workaround_bpiall_vbar1_sync_exception_sp_elx
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b report_unhandled_exception
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check_vector_size workaround_bpiall_vbar1_sync_exception_sp_elx
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vector_entry workaround_bpiall_vbar1_irq_sp_elx
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b report_unhandled_interrupt
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check_vector_size workaround_bpiall_vbar1_irq_sp_elx
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vector_entry workaround_bpiall_vbar1_fiq_sp_elx
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b report_unhandled_interrupt
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check_vector_size workaround_bpiall_vbar1_fiq_sp_elx
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vector_entry workaround_bpiall_vbar1_serror_sp_elx
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b report_unhandled_exception
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check_vector_size workaround_bpiall_vbar1_serror_sp_elx
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/* ---------------------------------------------------------------------
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* Lower EL using AArch64 : 0x400 - 0x600 (UNUSED)
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* ---------------------------------------------------------------------
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*/
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vector_entry workaround_bpiall_vbar1_sync_exception_aarch64
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b report_unhandled_exception
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check_vector_size workaround_bpiall_vbar1_sync_exception_aarch64
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vector_entry workaround_bpiall_vbar1_irq_aarch64
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b report_unhandled_interrupt
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check_vector_size workaround_bpiall_vbar1_irq_aarch64
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vector_entry workaround_bpiall_vbar1_fiq_aarch64
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b report_unhandled_interrupt
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check_vector_size workaround_bpiall_vbar1_fiq_aarch64
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vector_entry workaround_bpiall_vbar1_serror_aarch64
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b report_unhandled_exception
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check_vector_size workaround_bpiall_vbar1_serror_aarch64
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/* ---------------------------------------------------------------------
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* Lower EL using AArch32 : 0x600 - 0x800
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* ---------------------------------------------------------------------
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*/
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vector_entry workaround_bpiall_vbar1_sync_exception_aarch32
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/* Restore register state from the workaround context */
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ldp x2, x3, [sp, #CTX_CVE_2017_5715_OFFSET + CTX_CVE_2017_5715_QUAD0]
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ldp x4, x5, [sp, #CTX_CVE_2017_5715_OFFSET + CTX_CVE_2017_5715_QUAD2]
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ldp x6, x30, [sp, #CTX_CVE_2017_5715_OFFSET + CTX_CVE_2017_5715_QUAD4]
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/* Apply the restored system register state */
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msr scr_el3, x2
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msr spsr_el3, x3
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msr elr_el3, x4
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msr sctlr_el1, x5
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msr esr_el3, x6
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/*
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* Workaround is complete, so swap VBAR_EL3 to point
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* to workaround entry table in preparation for subsequent
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* Sync/IRQ/FIQ/SError exceptions.
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*/
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adr x2, workaround_bpiall_vbar0_runtime_exceptions
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msr vbar_el3, x2
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/*
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* Restore all GP regs except x0 and x1. The value in x0
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* indicates the type of the original exception.
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*/
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ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
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ldp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
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ldp x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6]
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ldp x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8]
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ldp x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10]
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ldp x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12]
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ldp x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14]
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ldp x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16]
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ldp x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18]
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ldp x20, x21, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X20]
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ldp x22, x23, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X22]
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ldp x24, x25, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X24]
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ldp x26, x27, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X26]
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ldp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28]
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/*
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* Each of these handlers will first restore x0 and x1 from
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* the context and the branch to the common implementation for
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* each of the exception types.
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*/
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tbnz x0, #1, workaround_bpiall_vbar1_irq
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tbnz x0, #2, workaround_bpiall_vbar1_fiq
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tbnz x0, #3, workaround_bpiall_vbar1_serror
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/* Fallthrough case for Sync exception */
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ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
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b sync_exception_aarch64
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check_vector_size workaround_bpiall_vbar1_sync_exception_aarch32
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vector_entry workaround_bpiall_vbar1_irq_aarch32
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b report_unhandled_interrupt
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workaround_bpiall_vbar1_irq:
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ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
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b irq_aarch64
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check_vector_size workaround_bpiall_vbar1_irq_aarch32
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vector_entry workaround_bpiall_vbar1_fiq_aarch32
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b report_unhandled_interrupt
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workaround_bpiall_vbar1_fiq:
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ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
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b fiq_aarch64
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check_vector_size workaround_bpiall_vbar1_fiq_aarch32
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vector_entry workaround_bpiall_vbar1_serror_aarch32
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b report_unhandled_exception
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workaround_bpiall_vbar1_serror:
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ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
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b serror_aarch64
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check_vector_size workaround_bpiall_vbar1_serror_aarch32
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