Marvin Hsu ce3c97c95b Tegra210B01: SE1 and SE2/PKA1 context save (atomic) ... This patch adds the implementation of the SE atomic context save sequence. The atomic context-save consistently saves to the TZRAM carveout; thus there is no need to declare context save buffer or map MMU region in TZRAM for context save. The atomic context-save routine is responsible to validate the context-save progress counter, where CTX_SAVE_CNT=133(SE1)/646(SE2), and the SE error status to ensure the context save procedure complete successfully. Change-Id: Ic80843902af70e76415530266cb158f668976c42 Signed-off-by: Marvin Hsu <marvinh@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>		2019-01-16 10:11:18 -08:00
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se_private.h	Tegra210B01: SE1 and SE2/PKA1 context save (atomic)	2019-01-16 10:11:18 -08:00
security_engine.c	Tegra210B01: SE1 and SE2/PKA1 context save (atomic)	2019-01-16 10:11:18 -08:00