227 lines
6.8 KiB
C
227 lines
6.8 KiB
C
/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef SE_PRIVATE_H
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#define SE_PRIVATE_H
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#include <stdbool.h>
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#include <security_engine.h>
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/*
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* PMC registers
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*/
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/* Secure scratch registers */
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#define PMC_SECURE_SCRATCH4_OFFSET 0xC0U
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#define PMC_SECURE_SCRATCH5_OFFSET 0xC4U
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#define PMC_SECURE_SCRATCH6_OFFSET 0x224U
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#define PMC_SECURE_SCRATCH7_OFFSET 0x228U
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#define PMC_SECURE_SCRATCH120_OFFSET 0xB38U
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#define PMC_SECURE_SCRATCH121_OFFSET 0xB3CU
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#define PMC_SECURE_SCRATCH122_OFFSET 0xB40U
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#define PMC_SECURE_SCRATCH123_OFFSET 0xB44U
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/*
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* AHB arbitration memory write queue
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*/
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#define ARAHB_MEM_WRQUE_MST_ID_OFFSET 0xFCU
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#define ARAHB_MST_ID_SE2_MASK (0x1U << 13)
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#define ARAHB_MST_ID_SE_MASK (0x1U << 14)
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/* SE Status register */
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#define SE_STATUS_OFFSET 0x800U
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#define SE_STATUS_SHIFT 0
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#define SE_STATUS_IDLE \
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((0U) << SE_STATUS_SHIFT)
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#define SE_STATUS_BUSY \
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((1U) << SE_STATUS_SHIFT)
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#define SE_STATUS(x) \
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((x) & ((0x3U) << SE_STATUS_SHIFT))
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/* SE config register */
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#define SE_CONFIG_REG_OFFSET 0x14U
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#define SE_CONFIG_ENC_ALG_SHIFT 12
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#define SE_CONFIG_ENC_ALG_AES_ENC \
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((1U) << SE_CONFIG_ENC_ALG_SHIFT)
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#define SE_CONFIG_ENC_ALG_RNG \
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((2U) << SE_CONFIG_ENC_ALG_SHIFT)
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#define SE_CONFIG_ENC_ALG_SHA \
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((3U) << SE_CONFIG_ENC_ALG_SHIFT)
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#define SE_CONFIG_ENC_ALG_RSA \
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((4U) << SE_CONFIG_ENC_ALG_SHIFT)
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#define SE_CONFIG_ENC_ALG_NOP \
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((0U) << SE_CONFIG_ENC_ALG_SHIFT)
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#define SE_CONFIG_ENC_ALG(x) \
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((x) & ((0xFU) << SE_CONFIG_ENC_ALG_SHIFT))
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#define SE_CONFIG_DEC_ALG_SHIFT 8
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#define SE_CONFIG_DEC_ALG_AES \
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((1U) << SE_CONFIG_DEC_ALG_SHIFT)
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#define SE_CONFIG_DEC_ALG_NOP \
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((0U) << SE_CONFIG_DEC_ALG_SHIFT)
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#define SE_CONFIG_DEC_ALG(x) \
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((x) & ((0xFU) << SE_CONFIG_DEC_ALG_SHIFT))
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#define SE_CONFIG_DST_SHIFT 2
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#define SE_CONFIG_DST_MEMORY \
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((0U) << SE_CONFIG_DST_SHIFT)
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#define SE_CONFIG_DST_HASHREG \
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((1U) << SE_CONFIG_DST_SHIFT)
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#define SE_CONFIG_DST_KEYTAB \
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((2U) << SE_CONFIG_DST_SHIFT)
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#define SE_CONFIG_DST_SRK \
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((3U) << SE_CONFIG_DST_SHIFT)
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#define SE_CONFIG_DST_RSAREG \
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((4U) << SE_CONFIG_DST_SHIFT)
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#define SE_CONFIG_DST(x) \
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((x) & ((0x7U) << SE_CONFIG_DST_SHIFT))
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/* DRNG random number generator config */
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#define SE_RNG_SRC_CONFIG_REG_OFFSET 0x344U
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#define DRBG_RO_ENT_SRC_SHIFT 1
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#define DRBG_RO_ENT_SRC_ENABLE \
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((1U) << DRBG_RO_ENT_SRC_SHIFT)
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#define DRBG_RO_ENT_SRC_DISABLE \
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((0U) << DRBG_RO_ENT_SRC_SHIFT)
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#define SE_RNG_SRC_CONFIG_RO_ENT_SRC(x) \
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((x) & ((0x1U) << DRBG_RO_ENT_SRC_SHIFT))
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#define DRBG_RO_ENT_SRC_LOCK_SHIFT 0
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#define DRBG_RO_ENT_SRC_LOCK_ENABLE \
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((1U) << DRBG_RO_ENT_SRC_LOCK_SHIFT)
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#define DRBG_RO_ENT_SRC_LOCK_DISABLE \
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((0U) << DRBG_RO_ENT_SRC_LOCK_SHIFT)
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#define SE_RNG_SRC_CONFIG_RO_ENT_SRC_LOCK(x) \
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((x) & ((0x1U) << DRBG_RO_ENT_SRC_LOCK_SHIFT))
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#define DRBG_RO_ENT_IGNORE_MEM_SHIFT 12
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#define DRBG_RO_ENT_IGNORE_MEM_ENABLE \
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((1U) << DRBG_RO_ENT_IGNORE_MEM_SHIFT)
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#define DRBG_RO_ENT_IGNORE_MEM_DISABLE \
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((0U) << DRBG_RO_ENT_IGNORE_MEM_SHIFT)
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#define SE_RNG_SRC_CONFIG_RO_ENT_IGNORE_MEM(x) \
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((x) & ((0x1U) << DRBG_RO_ENT_IGNORE_MEM_SHIFT))
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/* SE OPERATION */
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#define SE_OPERATION_REG_OFFSET 0x8U
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#define SE_OPERATION_SHIFT 0
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#define SE_OP_ABORT \
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((0x0U) << SE_OPERATION_SHIFT)
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#define SE_OP_START \
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((0x1U) << SE_OPERATION_SHIFT)
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#define SE_OP_RESTART \
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((0x2U) << SE_OPERATION_SHIFT)
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#define SE_OP_CTX_SAVE \
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((0x3U) << SE_OPERATION_SHIFT)
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#define SE_OP_RESTART_IN \
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((0x4U) << SE_OPERATION_SHIFT)
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#define SE_OPERATION(x) \
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((x) & ((0x7U) << SE_OPERATION_SHIFT))
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/* SE_CTX_SAVE_AUTO */
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#define SE_CTX_SAVE_AUTO_REG_OFFSET 0x74U
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/* Enable */
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#define SE_CTX_SAVE_AUTO_ENABLE_SHIFT 0
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#define SE_CTX_SAVE_AUTO_DIS \
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((0U) << SE_CTX_SAVE_AUTO_ENABLE_SHIFT)
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#define SE_CTX_SAVE_AUTO_EN \
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((1U) << SE_CTX_SAVE_AUTO_ENABLE_SHIFT)
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#define SE_CTX_SAVE_AUTO_ENABLE(x) \
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((x) & ((0x1U) << SE_CTX_SAVE_AUTO_ENABLE_SHIFT))
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/* Lock */
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#define SE_CTX_SAVE_AUTO_LOCK_SHIFT 8
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#define SE_CTX_SAVE_AUTO_LOCK_EN \
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((1U) << SE_CTX_SAVE_AUTO_LOCK_SHIFT)
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#define SE_CTX_SAVE_AUTO_LOCK_DIS \
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((0U) << SE_CTX_SAVE_AUTO_LOCK_SHIFT)
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#define SE_CTX_SAVE_AUTO_LOCK(x) \
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((x) & ((0x1U) << SE_CTX_SAVE_AUTO_LOCK_SHIFT))
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/* Current context save number of blocks */
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#define SE_CTX_SAVE_AUTO_CURR_CNT_SHIFT 16
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#define SE_CTX_SAVE_AUTO_CURR_CNT_MASK 0x3FFU
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#define SE_CTX_SAVE_GET_BLK_COUNT(x) \
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(((x) >> SE_CTX_SAVE_AUTO_CURR_CNT_SHIFT) & \
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SE_CTX_SAVE_AUTO_CURR_CNT_MASK)
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#define SE_CTX_SAVE_SIZE_BLOCKS_SE1 133
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#define SE_CTX_SAVE_SIZE_BLOCKS_SE2 646
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/* SE TZRAM OPERATION - only for SE1 */
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#define SE_TZRAM_OPERATION 0x540U
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#define SE_TZRAM_OP_MODE_SHIFT 1
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#define SE_TZRAM_OP_MODE_SAVE \
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((0U) << SE_TZRAM_OP_MODE_SHIFT)
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#define SE_TZRAM_OP_MODE_RESTORE \
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((1U) << SE_TZRAM_OP_MODE_SHIFT)
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#define SE_TZRAM_OP_MODE(x) \
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((x) & ((0x1U) << SE_TZRAM_OP_MODE_SHIFT))
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#define SE_TZRAM_OP_BUSY_SHIFT 2
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#define SE_TZRAM_OP_BUSY_OFF \
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((0U) << SE_TZRAM_OP_BUSY_SHIFT)
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#define SE_TZRAM_OP_BUSY_ON \
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((1U) << SE_TZRAM_OP_BUSY_SHIFT)
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#define SE_TZRAM_OP_BUSY(x) \
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((x) & ((0x1U) << SE_TZRAM_OP_BUSY_SHIFT))
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#define SE_TZRAM_OP_REQ_SHIFT 0
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#define SE_TZRAM_OP_REQ_IDLE \
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((0U) << SE_TZRAM_OP_REQ_SHIFT)
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#define SE_TZRAM_OP_REQ_INIT \
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((1U) << SE_TZRAM_OP_REQ_SHIFT)
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#define SE_TZRAM_OP_REQ(x) \
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((x) & ((0x1U) << SE_TZRAM_OP_REQ_SHIFT))
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/* SE Interrupt */
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#define SE_INT_STATUS_REG_OFFSET 0x10U
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#define SE_INT_OP_DONE_SHIFT 4
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#define SE_INT_OP_DONE_CLEAR \
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((0U) << SE_INT_OP_DONE_SHIFT)
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#define SE_INT_OP_DONE_ACTIVE \
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((1U) << SE_INT_OP_DONE_SHIFT)
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#define SE_INT_OP_DONE(x) \
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((x) & ((0x1U) << SE_INT_OP_DONE_SHIFT))
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/* SE error status */
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#define SE_ERR_STATUS_REG_OFFSET 0x804U
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/* SE linked list (LL) register */
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#define SE_IN_LL_ADDR_REG_OFFSET 0x18U
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#define SE_OUT_LL_ADDR_REG_OFFSET 0x24U
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#define SE_BLOCK_COUNT_REG_OFFSET 0x318U
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/* AES data sizes */
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#define TEGRA_SE_AES_BLOCK_SIZE 16
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#define TEGRA_SE_AES_MIN_KEY_SIZE 16
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#define TEGRA_SE_AES_MAX_KEY_SIZE 32
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#define TEGRA_SE_AES_IV_SIZE 16
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/*******************************************************************************
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* Inline functions definition
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******************************************************************************/
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static inline uint32_t tegra_se_read_32(const tegra_se_dev_t *dev, uint32_t offset)
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{
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return mmio_read_32(dev->se_base + offset);
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}
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static inline void tegra_se_write_32(const tegra_se_dev_t *dev, uint32_t offset, uint32_t val)
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{
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mmio_write_32(dev->se_base + offset, val);
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}
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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#endif /* SE_PRIVATE_H */
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