Soby Mathew 12d554f941 Rationalize UART usage among different BL stages ... This patch changes the UART port assignment for various BL stages so as to make it consistent on the platform ports. The BL1, BL2 and BL3-1 now uses UART0 on the FVP port and SoC UART0 on the Juno port. The BL3-2 uses UART2 on the FVP port and FPGA UART0 on the Juno port. This provides an interim fix to ARM-software/tf-issues#220 until support is added for changing the UART port for a BL image between cold boot and runtime. Change-Id: Iae5faea90be3d59e41e597b34a902f93e737505a		2014-08-21 16:30:25 +01:00
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common	Add CPU specific power management operations	2014-08-20 19:14:31 +01:00
fvp	Rationalize UART usage among different BL stages	2014-08-21 16:30:25 +01:00
juno	Rationalize UART usage among different BL stages	2014-08-21 16:30:25 +01:00