Soby Mathew b1a9631d81 Optimize barrier usage during Cortex-A57 power down ... This the patch replaces the DSB SY with DSB ISH after disabling L2 prefetches during the Cortex-A57 power down sequence. Change-Id: I048d12d830c1b974b161224eff079fb9f8ecf52d		2014-10-29 17:38:56 +00:00
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aarch64	Optimize barrier usage during Cortex-A57 power down	2014-10-29 17:38:56 +00:00
cpu-errata.mk	Add support for selected Cortex-A57 errata workarounds	2014-08-20 19:14:31 +01:00