Heyi Guo 612b4a3f2d drivers/gicv3: also shift eSPI register offset in GICD_OFFSET_64() ... ESPI register offset should also be shifted right by REG##R_SHIFT to keep consistent. It is not a functional issue, for GICD_OFFSET_64() is only used for GICD_IROUTER<E>, and IROUTER_SHIFT is 0. Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com> Change-Id: I76eee5c50e4300890e78e80bddde135ce88daa2d		2021-02-03 11:12:30 +00:00
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arm_gicv3_common.c	Sanitise includes across codebase	2019-01-04 10:43:17 +00:00
gic-x00.c	GIC-600: Fix MISRA-2012 defects	2020-07-29 16:51:05 +00:00
gic600_multichip.c	GIC-600: Fix include ordering according to the coding style	2019-11-19 11:38:33 +00:00
gic600_multichip_private.h	gic multichip: add support for clayton	2020-04-07 18:41:13 +05:30
gicdv3_helpers.c	TF-A GICv3 driver: Add extended PPI and SPI range	2020-04-06 16:27:54 +01:00
gicrv3_helpers.c	TF-A GICv3 driver: Change API for GICR_IPRIORITYR accessors	2020-04-07 18:40:44 +01:00
gicv3.mk	GICv3: GIC-600: Detect GIC-600 at runtime	2020-06-09 17:05:49 +00:00
gicv3_helpers.c	drivers/gicv3: add debug log for maximum INTID of SPI and eSPI	2021-02-03 11:12:24 +00:00
gicv3_main.c	drivers/gicv3: fix logical issue for num_eints	2021-02-03 11:12:13 +00:00
gicv3_private.h	drivers/gicv3: also shift eSPI register offset in GICD_OFFSET_64()	2021-02-03 11:12:30 +00:00