Soby Mathew 663db206f8 Derive stack alignment from CACHE_WRITEBACK_GRANULE ... The per-cpu stacks should be aligned to the cache-line size and the `declare_stack` helper in asm_macros.S macro assumed a cache-line size of 64 bytes. The platform defines the cache-line size via CACHE_WRITEBACK_GRANULE macro. This patch modifies `declare_stack` helper macro to derive stack alignment from the platform defined macro. Change-Id: I1e1b00fc8806ecc88190ed169f4c8d3dd25fe95b		2016-07-08 09:58:10 +01:00
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aarch64	Derive stack alignment from CACHE_WRITEBACK_GRANULE	2016-07-08 09:58:10 +01:00
plat_bl1_common.c	FWU: Pass client cookie to FWU_SMC_UPDATE_DONE	2015-12-15 14:33:25 +00:00
plat_gic.c	Refactor fvp gic code to be a generic driver	2014-07-09 16:36:39 +01:00
plat_gicv2.c	Prepare platforms to use refactored ARM GIC drivers	2015-12-09 09:56:53 +00:00
plat_gicv3.c	Prepare platforms to use refactored ARM GIC drivers	2015-12-09 09:56:53 +00:00