Andre Przywara c520be4b3a allwinner: Relax PSCI entry point check ... The DRAM controller supports up to 4GB of DRAM, and there are actually boards out there where we can use at least 3GB of this. Relax the PSCI entry point check, to be not restricted to 2GB of DRAM. Signed-off-by: Andre Przywara <andre.przywara@arm.com>		2018-06-28 23:47:30 +01:00
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allwinner	allwinner: Relax PSCI entry point check	2018-06-28 23:47:30 +01:00
arm	ARM platforms: Initialize cntfrq for BL1 Firmware update	2018-06-26 15:55:46 +01:00
common	DynamIQ: Enable MMU without using stack	2018-06-27 11:31:30 +01:00
compat	Do not enable SVE on pre-v8.2 platforms	2017-11-30 17:45:23 +00:00
hisilicon	Make TF UUID RFC 4122 compliant	2018-06-14 14:41:00 +01:00
imx	Support for NXP's i.MX8QM SoC	2018-06-19 10:24:32 +08:00
layerscape	layerscape: fix integer handling issues	2018-04-11 12:12:24 +00:00
mediatek	Make TF UUID RFC 4122 compliant	2018-06-14 14:41:00 +01:00
nvidia/tegra	types: use int-ll64 for both aarch32 and aarch64	2018-04-27 18:35:02 +09:00
qemu	Merge pull request #1334 from michpappas/tf-issues#572_qemu_dont_use_C_for_crash_console	2018-04-03 11:59:55 +01:00
rockchip	Merge pull request #1406 from robertovargas-arm/uuid	2018-06-22 15:56:42 +01:00
rpi3	rpi3: add OPTEE support	2018-06-19 16:40:22 +08:00
socionext	synquacer: Add platform makefile and documentation	2018-06-21 14:18:37 +05:30
ti/k3	ti: k3: Introduce basic generic board support	2018-06-19 12:42:37 -05:00
xilinx/zynqmp	Merge pull request #1406 from robertovargas-arm/uuid	2018-06-22 15:56:42 +01:00