Arunachalam Ganapathy 68ac5ed049 fix(el3_runtime): fix SVE and AMU extension enablement flags ... If SVE are enabled for both Non-secure and Secure world along with AMU extension, then it causes the TAM_BIT in CPTR_EL3 to be set upon exit from bl31. This restricts access to the AMU register set in normal world. This fix maintains consistency in both TAM_BIT and CPTR_EZ_BIT by saving and restoring CPTR_EL3 register from EL3 context. Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> Change-Id: Id76ce1d27ee48bed65eb32392036377716aff087		2021-07-23 10:33:59 +01:00
..
aarch32	fix: random typos in tf-a code base	2021-06-03 09:31:10 +02:00
aarch64	fix(el3_runtime): fix SVE and AMU extension enablement flags	2021-07-23 10:33:59 +01:00
cpu_data_array.c	Sanitise includes across codebase	2019-01-04 10:43:17 +00:00