Louis Mayencourt cba71b70ef Cortex-A35: Implement workaround for errata 855472 ... Under specific conditions, the processor might issue an eviction and an L2 cache clean operation to the interconnect in the wrong order. Set the CPUACTLR.ENDCCASCI bit to 1 to avoid this. Change-Id: Ide7393adeae04581fa70eb9173b742049fc3e050 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>		2019-04-17 13:46:43 +01:00
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arch	aarch32: Allow compiling with soft-float toolchain	2019-04-05 11:37:19 +01:00
bl1	BL1: Enable pointer authentication support	2019-02-27 11:58:09 +00:00
bl2	BL2_AT_EL3: Enable pointer authentication support	2019-02-27 11:58:09 +00:00
bl2u	Standardise header guards across codebase	2018-11-08 10:20:19 +00:00
bl31	BL31: Enable pointer authentication support	2019-02-27 11:58:10 +00:00
bl32	TSP: Enable pointer authentication support	2019-02-27 11:58:10 +00:00
common	Merge pull request #1751 from vwadekar/tegra-scatter-file-support	2019-03-01 11:23:58 +00:00
drivers	cot-desc: optimise memory further	2019-04-08 14:24:21 +01:00
dt-bindings	stm32mp1: update device tree files	2019-01-18 15:45:08 +01:00
lib	Cortex-A35: Implement workaround for errata 855472	2019-04-17 13:46:43 +01:00
plat	Mbed TLS: Remove weak heap implementation	2019-04-12 09:52:52 +01:00
services	Remove support for the SMC Calling Convention 2.0	2019-01-30 16:01:49 +00:00
tools_share	Sanitise includes across codebase	2019-01-04 10:43:17 +00:00