Dan Handley ce4c820d8c Remove use of PLATFORM_CACHE_LINE_SIZE ... The required platform constant PLATFORM_CACHE_LINE_SIZE is unnecessary since CACHE_WRITEBACK_GRANULE effectively provides the same information. CACHE_WRITEBACK_GRANULE is preferred since this is an architecturally defined term and allows comparison with the corresponding hardware register value. Replace all usage of PLATFORM_CACHE_LINE_SIZE with CACHE_WRITEBACK_GRANULE. Also, add a runtime assert in BL1 to check that the provided CACHE_WRITEBACK_GRANULE matches the value provided in CTR_EL0. Change-Id: If87286be78068424217b9f3689be358356500dcd		2015-04-27 18:05:06 +01:00
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aarch64	Add support to indicate size and end of assembly functions	2015-04-08 13:02:59 +01:00
drivers/pwrc	Move bakery algorithm implementation out of coherent memory	2015-01-22 10:57:44 +00:00
include	Remove use of PLATFORM_CACHE_LINE_SIZE	2015-04-27 18:05:06 +01:00
tsp	Remove coherent memory from the BL memory maps	2015-01-22 10:57:44 +00:00
bl1_fvp_setup.c	Remove coherent memory from the BL memory maps	2015-01-22 10:57:44 +00:00
bl2_fvp_setup.c	Remove use of PLATFORM_CACHE_LINE_SIZE	2015-04-27 18:05:06 +01:00
bl31_fvp_setup.c	Remove coherent memory from the BL memory maps	2015-01-22 10:57:44 +00:00
fvp_def.h	Use ARM CCI driver on FVP and Juno platforms	2015-03-16 18:37:59 +00:00
fvp_io_storage.c	TBB: authenticate BL3-x images and certificates	2015-01-28 18:27:54 +00:00
fvp_pm.c	Use ARM CCI driver on FVP and Juno platforms	2015-03-16 18:37:59 +00:00
fvp_private.h	Use ARM CCI driver on FVP and Juno platforms	2015-03-16 18:37:59 +00:00
fvp_security.c	FVP: map non-secure DRAM1 in the MMU	2015-01-21 09:44:40 +00:00
fvp_topology.c	Export maximum affinity using PLATFORM_MAX_AFFLVL macro	2015-02-12 15:12:52 +00:00
fvp_trusted_boot.c	TBB: add a platform specific function to validate the ROTPK	2015-01-28 18:26:59 +00:00
platform.mk	Use ARM CCI driver on FVP and Juno platforms	2015-03-16 18:37:59 +00:00