Varun Wadekar cf3ed0dcc7 cpus: denver: reset power state to 'C1' on boot ... Denver CPUs expect the power state field to be reset to 'C1' during boot. This patch updates the reset handler to reset the ACTLR_.PMSTATE field to 'C1' state during CPU boot. Change-Id: I7cb629627a4dd1a30ec5cbb3a5e90055244fe30c Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>		2018-09-04 17:33:56 -07:00
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aem_generic.h	Use SPDX license identifiers	2017-05-03 09:39:28 +01:00
cortex_a35.h	Use SPDX license identifiers	2017-05-03 09:39:28 +01:00
cortex_a53.h	CPU: Correct names of implementation-defined aux regs	2017-08-29 13:52:48 +01:00
cortex_a55.h	Add support for Cortex-A75 and Cortex-A55 CPUs	2017-06-01 11:44:52 +01:00
cortex_a57.h	Implement static workaround for CVE-2018-3639	2018-05-23 12:45:48 +01:00
cortex_a72.h	lib: cpu: Add L2 cache aux control register definition to CA72	2018-07-18 18:48:30 +03:00
cortex_a73.h	Implement static workaround for CVE-2018-3639	2018-05-23 12:45:48 +01:00
cortex_a75.h	Implement static workaround for CVE-2018-3639	2018-05-23 12:45:48 +01:00
cortex_a76.h	Implement dynamic mitigation for CVE-2018-3639 on Cortex-A76	2018-06-08 11:46:31 +01:00
cortex_ares.h	Implement Cortex-Ares 1043202 erratum workaround	2018-06-08 11:46:31 +01:00
cortex_deimos.h	Add initial CPU support for Cortex-Deimos	2018-07-11 13:26:48 +01:00
cortex_helios.h	Add initial CPU support for Cortex-Helios	2018-07-11 13:26:52 +01:00
cpu_macros.S	Remove integrity check in declare_cpu_ops_base	2018-07-11 09:23:04 +01:00
cpuamu.h	Refactor AMU support for Cortex A75	2018-02-27 13:28:41 +00:00
denver.h	cpus: denver: reset power state to 'C1' on boot	2018-09-04 17:33:56 -07:00
dsu_def.h	DSU erratum 936184 workaround	2018-08-17 10:34:43 +01:00