b8e637f49e
This patch does not change code, it only updates comments and macro name for 6th bit of Status Register. So TF-A binary stay same. 6th bit of the Status Register is named TX EMPTY and is set to 1 when both Transmitter Holding Register (THR) or Transmitter Shift Register (TSR) are empty. It is when all characters were already transmitted. There is also TX FIFO EMPTY bit in the Status Register which is set to 1 only when THR is empty. In both console_a3700_core_init() and console_a3700_core_flush() functions we should wait until both THR and TSR are empty therefore we should check 6th bit of the Status Register. So current code is correct, just had misleading macro names and comments. This change fixes this "documentation" issue, fixes macro name for 6th bit of the Status Register and also updates comments. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I19e4e7f53a90bcfb318e6dd1b1249b6cbf81c4d3 |
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| a3700_console.h | ||