johpow01 e26c59d2c9 Workaround for Cortex A78 erratum 1941498 ... Cortex A78 erratum 1941498 is a Cat B erratum that applies to revisions r0p0, r1p0, and r1p1. The workaround is to set bit 8 in the ECTLR_EL1 register, there is a small performance cost (<0.5%) for setting this bit. SDEN can be found here: https://documentation-service.arm.com/static/5fb66157ca04df4095c1cc2e Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I959cee8e3d46c1b84ff5e4409ce5945e459cc6a9		2021-01-12 18:06:37 +00:00
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aarch32	Cortex A9:errata 794073 workaround	2019-04-12 10:10:32 +00:00
aarch64	Workaround for Cortex A78 erratum 1941498	2021-01-12 18:06:37 +00:00
cpu-ops.mk	Workaround for Cortex A78 erratum 1941498	2021-01-12 18:06:37 +00:00
errata_report.c	Coverity: remove unnecessary header file includes	2020-02-04 10:23:51 -06:00