Sandrine Bailleux 85d80e5578 Initialize VTTBR_EL2 when bypassing EL2 ... In the situation that EL1 is selected as the exception level for the next image upon BL31 exit for a processor that supports EL2, the context management code must configure all essential EL2 register state to ensure correct execution of EL1. VTTBR_EL2 should be part of this set of EL2 registers because: - The ARMv8-A architecture does not define a reset value for this register. - Cache maintenance operations depend on VTTBR_EL2.VMID even when non-secure EL1&0 stage 2 address translation are disabled. This patch initializes the VTTBR_EL2 register to 0 when bypassing EL2 to address this issue. Note that this bug has not yet manifested itself on FVP or Juno because VTTBR_EL2.VMID resets to 0 on the Cortex-A53 and Cortex-A57. Change-Id: I58ce2d16a71687126f437577a506d93cb5eecf33		2015-12-09 11:34:10 +00:00
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aarch64	Initialize VTTBR_EL2 when bypassing EL2	2015-12-09 11:34:10 +00:00
cpus/aarch64	Juno R2: Configure the correct L2 RAM latency values	2015-11-19 14:53:58 +00:00
bakery_lock.h	Re-design bakery lock memory allocation and algorithm	2015-09-11 16:19:21 +01:00
cassert.h	Make CASSERT() macro callable from anywhere	2015-10-19 08:52:35 +01:00
mmio.h	Add mmio utility functions	2015-08-05 19:55:06 +08:00
semihosting.h	Remove variables from .data section	2014-05-06 17:55:38 +01:00
spinlock.h	Always use named structs in header files	2014-05-06 13:57:48 +01:00