Varun Wadekar e0d913c786 Add macros for retention control in Cortex-A53/A57 ... This patch adds macros suitable for programming the Advanced SIMD/Floating-point (only Cortex-A53), CPU and L2 dynamic retention control policy in the CPUECTLR_EL1 and L2ECTLR registers. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>		2015-08-24 21:30:21 +05:30
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aarch64	Add macros for retention control in Cortex-A53/A57	2015-08-24 21:30:21 +05:30