Vikram Kanigiri e3616819a9 Tegra: Perform cache maintenance on video carveout memory ... Currently, the non-overlapping video memory carveout region is cleared after disabling the MMU at EL3. If at any exception level the carveout region is being marked as cacheable, this zeroing of memory will not have an affect on the cached lines. Hence, we first invalidate the dirty lines and update the memory and invalidate again so that both caches and memory is zeroed out. Change-Id: If3b2d139ab7227f6799c0911d59e079849dc86aa		2015-09-14 22:09:40 +01:00
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aarch64	Tegra210: wait for 512 timer ticks before retention entry	2015-08-24 21:34:28 +05:30
drivers	Tegra: Perform cache maintenance on video carveout memory	2015-09-14 22:09:40 +01:00
tegra_bl31_setup.c	Tegra: memmap the actual memory available for BL31	2015-08-11 14:20:14 +05:30
tegra_common.mk	Tegra: T210: include CPU files from SoC's platform.mk	2015-07-24 09:08:27 +05:30
tegra_delay_timer.c	Tegra: introduce delay timer support	2015-07-17 19:06:36 +05:30
tegra_gic.c	Add missing features to the Tegra GIC driver	2015-06-22 14:55:49 +05:30
tegra_pm.c	Tegra: implement per-SoC validate_power_state() handler	2015-07-24 09:08:27 +05:30
tegra_sip_calls.c	Tegra: Support for Tegra's T132 platforms	2015-07-24 09:25:23 +05:30
tegra_topology.c	Support for NVIDIA's Tegra T210 SoCs	2015-05-29 16:43:25 +05:30